Chapter 4: UEFI BIOS
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UEFI ARM Mirror (Only available when "Mirror Mode" is set to Disabled and
"ADDDC Sparing" is set to Disabled)
Select Enabled to mimic behavior of UEFI-based ARM (Address Range Mirror) with setup
options to increase memory security, but it will reduce the memory capacity into half. The
options are Disabled and Enabled.
(UEFI) ARM Mirror Percentage (Available if "UEFI ARM Mirror" is set to Enabled)
Use this feature to set the percentage of memory space to be used for UEFI ARM mirroring
for memory security enhancement.Correctable Error Threshold
Use this feature to enter the threshold value for correctable memory errors. The default
setting is 512.
Leaky Bucket Low Bit
Use this feature to set the Low Bit value for the Leaky Bucket algorithm which is used to
check the data transmissions between CPU sockets and the memory controller. The default
setting is 11.
Leaky Bucket High Bit
Use this feature to set the High Bit value for the Leaky Bucket algorithm which is used to
check the data transmissions between CPU sockets and the memory controller. The default
setting is 14.
Partial Cache Line Sparing (PCLS)
Select Enabled to support partial cache line sparing, which will allow partial of data
contained in a cache line to be copied in the cache memory for safe-keeping/data security.
The options are Disabled and Enabled.
ADDDC (Adaptive Double Device Data Correction) Sparing
Select Enable for Adaptive Double Device Data Correction (ADDDC) support, which will
not only provide memory error checking and correction but will also prevent the system
from issuing a performance penalty before a device fails. Please note that virtual lockstep
mode will only start to work for ADDDC after a faulty DRAM module is spared. The options
are Enabled and Disabled.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected in a memory module and send the corrections to the requestor (the original
source). When this feature is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Enabled, Disabled, and Enable at End of POST (Power_On Self Test).
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