Chapter 4: BIOS
85
Data Scrambling for DDR4
Use this feature to enable or disable data scrambling for DDR4 memory. The options
are Auto, Disable, and Enable.
2x Refresh Enable
Use this feature to enable 2x memory refresh support to enhance memory performance.
The options are Auto, Disable, and Enable.
Memory Topology
This feature displays the information of memory modules detected by the BIOS.
Memory RAS Conguration Setup
Enabled Pcode WA for SAI PG
Use this feature to enable Pcode Work Around for SAI Policy group for A Step. The
options are Disabled and Enabled.
Mirror Mode
This feature allows memory to be mirrored between two channels, providing 100%
redundancy. The options are Disable, Full Mirror Mode, and Partial Mirror Mode.
UEFI ARM Mirror
This feature allows the system to imitate the bahavior of the UEFI based Address
Range Mirror with setup option. The options are Disabled and Enabled.
Correctable Error Threshold
Use this feature to specify the threshold value for correctable memory-error logging,
which sets a limit on the maximum number of events that can be logged in the memory
error log at a given time. The default setting is 512.
Partial Cache Line Sparing PCLS
Use this feature to enable or disable Partial Cache Line Sparing (PCLS). The options
are Disabled and Enabled.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Disabled, Enabled, and Enable at End of POST.
To Next Page
Loading...
