Supermicro X12STL-F - Page 45

45
Chapter 2: Installation
BMC
JPG1
JWD1
I-SGPIO1
I-SGPIO2
M.2-P
M.2 NVME
I-SATA4
I-SATA3
I-SATA2
MEGERAC
LICENCE
BT1
CPU SLOT6 PCIe 4.0 x8 (IN x16)
PCH SLOT4 PCIe 3.0 x2 (IN x4)
CPU SLOT5 PCIe 4.0 x8
JBT1
REV:1.01
X12STL-F
JUIDB1
LED1
LEDM1
JPCIE7
FAN4
COM2
USB2/3
JIPMB1
JPME2
JPWR2
JPWR1
JPI2C1
JF1
USB6/7 (3.0)
JL1
JSD2
JSD1 USB8(3.0)
LED4
LED3
JSTBY1
FAN1FAN2
FAN3
FANAFANB
I-SATA1
I-SATA0
JPCIE6
JPCIE5
JPCIE4
JPCIE5
MH10
MH11
JTPM1
CPU SLOT7 PCIe 4.0 x4 (IN x8)
DIMMB1 DIMMA2 DIMMB2 DIMMA1
USB0/1
BMC_LAN
COM1
VGA
LAN2
LAN1
USB4/5
I-SATA5
CHASSIS INTRUSION
PWRI2C
DESIGNED IN USA
M.2
CPU
Chassis Intrusion
A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable
from the chassis to inform you of a chassis intrusion when the chassis is opened. Refer to
the table below for pin denitions.
Chassis Intrusion

Pin# 
1 Intrusion Input
2 Ground
1
1. Chassis Intrusion
2. I-SGPIO1/2
SGPIO Headers
Two Serial Link General Purpose Input/Output headers (I-SGPIO1, I-SGPIO2) are located on
the motherboard. They are used to communicate with the enclosure management chip on the
backplane support the onboard I-SATA 3.0 ports. Refer to the table below for pin denitions.
S-SGPIO Header

Pin#  Pin# 
1 NC 2 NC
3 Ground 4 Data
5 Load 6 Ground
7 Clock 8 NC
NC = No Connection
2