Supermicro X13SAE - Page 76

Super X13SAE/X13SAE-F User's Manual
76
• SMX/TXT
• 64-bit
• EIST Technology
• CPU C3 state
• CPU C6 state
• CPU C7 state
• CPU C8 state
• CPU C9 state
• CPU C10 state
• Performance L1 Data Cache
• Performance L1 Instruction Cache
• Performance L2 Cache
• Performance L3 Cache
• Performance L4 Cache
• E󰀩cient L1 Data Cache
• E󰀩cient L1 Instruction Cache
• E󰀩cient L2 Cache
• E󰀩cient L3 Cache
• E󰀩cient L4 Cache
C6DRAM
This feature enables moving DRAM contents to PRM memory when the CPU is in a C6
state. The options are Disabled and Enabled.
Hardware Prefetcher
If set to Enabled, the hardware prefetcher will prefetch streams of data and instructions
from the main memory to the L2 cache to improve CPU performance. The options are
Disabled and Enabled.
Adjacent Cache Line Prefetch
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enabled.