Teac FD-55 Series - 268

Bit cells
1
o o
o
I 1 I
D
MFM
FDD WRITE/READ
MFM data window
4/3F (6 s)
tl
t2 (2lJs) I
(50% of data cycle)
Note: The above timings (JJs) are for FO-55A ~ F.
a half of the indicated values.
Bit cell (4l.Js)
1
1
o
1 o
D
D D
2F (4Us)
Timings for FO-55G are
(Fig.220) Bit correspondance and data window in the MFM method
Lt is important for the PLO circuit to generate an accurate window as
possible to obtain the widest window margin for data reading. It is
therefore necessary that the PLO does not respond to bit shift caused
by the read output peak shift from the magnetic head. It must be
designed to respond slowly so that the data window will be phase-locked
during several synchronizing bytes at the head of 10 field or data
field.
Write pre-compensation is generally used as the active compensation
method for the bit shift which contributes to the window margin
effectively. Since the direction of bit shift can be predicted by the
bit pattern, the position of the flux transition can be shifted in the
opposite direction in anticipation.
However, the degree of bi~ shift during read operation depends largely
on the overall frequency characteristics of the FOD system and the most
appropriate value of write pre-compensation should be determined for
each FDD and disko Large pre-compensation value results in undesirable
effects such as an increase in bit shift at the outer tracks, decrease
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