Technics SL-P111 - Page 24

@ TERMINAL FUNCTION OF LSI
e MN6617 (Digital Signal Processing : EFM Decoder, Error Correction, CLV Servo)
© AN8370S (Optical Servo Control)
=7
Pi : F i ; Pi ;
No-
Mark
v0
Function
Function
Hes
Mark
vO
Function
re
Mark
vo
|
Function
eae Es + ———
‘ Control input (FOON: Focus servo ON
1
|
BLKCK
Oo
ne
eas
block
(Q
data)
clock
DAS
O
1G
bic
deta
ournurihocused)
1
|
VEE
\
Power
supply
(connected
to
—5V)
22
|CNT1
'
au
' . Control input (TRON: Tracki ON
ALOK [ Sub-code frame (Q data) clock 2 {LSA | Phase difference input (A) 23 | CNT2 signal) eae Sec oe
2
|
CLOCK
Oo
(7.35
kHz)
DA7
(@)
16-bit
data
output
(Not
used)
Control
input
(KICKF:
Kick
directi
+
:
3
|
GND
1
|
GND
terminal
24
|CNT3
i
powaicneaa
ee
- Q dat tput .
as ake ie] Sub-code (Q data) outpu DA6 1/0 16-bit data output (Not used) as lees phuss ditarehesinpue ie) B65. TONTA Control input (KICKR: Kick direction
4
CRC
re)
Sub-code
(Q
data)
CRC
check
P
jo
|
[Reverse]
command)
| (Not used, open! DA5 Oo 16-bit data output (Not used) APC fe) Auto laser power control output 26 | FLOCK 1] Focus lock signal output
5
RST
|
Reset
signal
input
{reset
at
‘L"’)
|
aI
Capacitor
connection
for
inversion
RF
high
—+— + i i 27 ‘-FBD oO i
6
MLD
\
Cani@sad
loadinout
DA4
fo)
16-bit
data
output
(Not
used)
TEOUT
Oo
Tracking
error
signal
output
Cc
O
speed
detection
i tion for i i FI
|
[-
TEG
|
Tracking
error
gain
adjusting
input
28
|C-SBDO
oO
Canecitor
connection
(or
ijversion
RE
IOW
7
MCLK
|
Command
clock
input
speed
detection
DA3 fe) 16-bit data output (Not used) ; F : ;
T + , . Capacitor connection for non-inversion RF
8
MDATA
!
Command
data
input
TE+
I
Phase
difference-to-voltage
conversion
(+)
29
|
C-SBRT
oO
low
speed
detection
| | a ; 4 —— : aT
5 t t f = RF
9
|
DMUTE
Muting
control
(muting
ON
at
“H"")
|
|
40
|
OA2
.
TSE
dare
BUIPON
NOE
use
TE-
|_|
Phase
difference-to-voltage
conversion
(—)
80
|CFBRT
||.
0,
~
|
papene
sane
ar
ae
pensineron
+—-
poe i ; |
10
TRON
I
ae
ene
oe
oem
41
DAI
ie)
16-bit
data
output
(Not
used)
APC—
|
Laser
power
inversion
input
31.
|
RF
OUT
oO
RF
signal
output
r
if
T
1
;
Capacitor
connection
for
phase
difference
r
i
i iti C-MEM | 32. |BDO ie) Drop-out detection output
11. | STAT O ia eC Oe. 42 | DAO re) 16-bit data output (Not used) memory
T
7
t
T
1
APC+
1
Laser
power
input
|
33.
|RFIN
|
RF
signal
input
12 SMCK ie) Clock output (4.2336 MHz) 43 D7
] | Pitch contro! clock output = Ba ue PROM Bers output VREF oO Reference current generation 34 | S-OUT ie) Focus search signal output
is AMEE 2 (Not used, open) T + — Capacitor connection for triangular wave
+
t
51
RAMOE
16
K
RAM
OE
signal
SENSE
fe}
Selector
output
(track-crossed)
35
|
C-LW
|
generation
J
Track counter input signal ie es
14
ITC
!
(Not
used,
open)
52
RAMWE
16
K
RAM
WE
signa!
HIN
|
Tracking
hold
circuit
input
36
daca
fe)
Focus
error
signal
output
~— +
ae Test mode selection 53 RAMA 0 : : Da : ae
15 | TEST ! 16 K RAM address signal 16 | HOUT (e) Tracking hold circuit output 37 |FEG ! Focus error gain adjusting input
(Not used, connected to +5V) 4 Loe ie) (RAMAO : LSB, RAMA10: MSB)
16
|
x2
fe)
Clock
output
(16.9344
MHz)
SPCNT
eral
yo
speed
control
output
(not
used,
38
|
FE-REF
I
Focus
error
comparison
voltage
generation
Spindle motor ON signal aa ; z - weave
lock
input
(16.9344
MHz)
(ON
at
’L"’)
‘|
rack-cross
reference
speed
setting
y
é
17 | x1 ! Clock inpu C-MSP cangeitor connection (nat uaed:open) 39 |PDB \ Photo detector current input (B)
Hel ial selecti indl jotor drive signal ;
2) Scr cla 42 ee rie [oar [1 |aweteriersnrsomecn | | [ve | 0 [Gotti omen
—+ | Spindle motor FG signal input Pa i = oh
O L channel deglitch signal | 20 | KICK Lo | Track kick signal output 41 |IVA fe) Current to voltage conversion (A)
Eas (Not used) ee
20 ROG fe) Clock output (Spindle motor control) POET SUPDIV ICANN CIO Toc Sy) ae eee RhotordeledtoC current ABUL UA)
De-emphasis ON signal | Power supply (Connected to +5V)
21 DEMPH oO (de-emphasis ON at ‘'H’’) t- + ——>
70 PD —— .
Interpolation flag f + © AN8371S (Data slice and PLL)
22 IPFLAG Q (interpolation at ‘’H’’) 71 PCKO _—
4
4
t
+
-
23 | FLAGO {e) Error flag (error at ‘’H"’) 72 | ecK | PLL extract clock input Function ie Mark VO | Function
16 K RAM address reset signal r t + ; ;
24 FLAG6 ie) hea at oH") ls 73 VDD I Power supply (connected to +5V) Power supply (connected to —5V) 13 | PL2 | PLL loop filter constant connection
+ + +. _ +. +
25 | xcK O Clock (16.9344 MHz) output 74 EFM I | EFM signal input (PLL) RF signal output data-sliced into digital value 14 | FPC | Frequency comparison error signal input
T AG 1 | SRF | ; iis EFM signal'nput (OSE) EFM signal output synchronized with PCK 15 | RF I RF signal input
26 DA15 Oo 16-bit data output 76 po { Drop-out signal (Drop-out at ‘'H’’) 7
| + I + GND terminal (digital system) 16 | ARF Oo RF signal output with AGC applied
77
CLVS
|
11T
servo
OK
signal
(OK
at
‘‘H"’)
4
a4
: Not used : :
a! PA . ap Eresereulee Neh yene! ae . Clock output extracted from SRF 17°. | AGC I ARF signal input for AGC drop-out detection
7
a
78
|
FPC
PLL
frequency
comparision
signal
Le
4 ene +
28 DA13 ie) 16-bit data output PLL frequency in take operation Power supply (connected to +5V) 18 | AC | AGC loop filter constant connection
7 1 - aii ‘ 4 sional: (Not used) VCO free ran frequency adjusting current |
aa
=
:
:
t
19
|DO
Oo
Drop-out
detection
pulse
output
29 DA12 10] 16-bit data output (Not used) 80 SRFO = inpu 1
_—_ 4 Capacitor connection for VCO oscillation ;
T : ; 81 | NSRF frequency 1on 20 | A-GND | GND terminal (analog system)
30 DA11 ie) 16-bit data output (Not used Elis ae 7 : - —-
+
82
|
RF
—
|
feaneayy
Sean
Scoearee
21
|DSL
|_|
RF
signal
input
for
data
slicer
31
GND
!
Teno
terminal
:
;
-
ae
- 83 SUBC fe) Sub-code seria! output data ely fOr Ee eoniatien 22 | SLC | Stice level control signal input
32 DAi0O 0 16-bit data output (Not used) +
aE
T
1
i
Clock
for
sub-code
serial
output
Capacitor
connection
for
PLL
DO
protection
23.
|
FC1
|
Data
slicer
filter
capacitor
connection
33 DAQ ie) 16-bit data output (Not used) E SBCK | (Not used)
aj i: 1 1 PLL loop filter constant connection 24 |FC2 | I Data slicer filter capacitor connection
— 33 —
— 34 -—
° MN15261PDU (
7 7
Pi
ee Mark Signal
1 VSs GND
2 xO —
3 | XI SENSE
4 Poo PC
- =
5 P01 M DATA
Bs
6 Po2 MCLK
—
7 PO3 MLD
[a=
8 P10 MRLY
fs pees
9 P14 D-DAT
10 P12 SYNC
11 | P13 D-DP
12 SYNC —
a
13 RST RESET
14 IRQ BLKCK
15 P50
t KEY
18 P53
19 SBT CLDCK
20 SBD SUBQ
21 P20 TGC
22 P21 TRV-H
23 P22 TRV-R
24 P23 TRV-F
25 P30 CNT4
© MN1550PDT (
n i?) iS)
<
oO oO
OSCc1
ST
SMCK