Theory of Operation-2213 Service
and a voltage divider composed of R645 and R646 establish
the charging voltage of holdoff timing capacitors C645,
C646, and C647. The capacitor (or combination of
capacitors) used is switched into the holdoff circuit by
contacts on S630B, the SEC/DIV timing switch.
During holdoff time, while U640B pin 9 remains LO,
the output of U607C will be HI. Inverter U607B will invert
the HI to a LO logic level that is then applied to the Reset
inputs of both U603A and U603B at pins 1 and 13 respec
tively. The LO at these inputs holds both flip-flops in the
reset state, with the Q outputs HI and Q outputs LO. In
the reset state, flip-flops U603A and U603B will not
respond to input trigger signals. The Set input of U603B is
held HI by the output of U607A and does not affect flip-
flop operation. (With AUTO trigger mode selected, a
different condition at the Set input of U603B occurs when
triggering signals are not received; see "Auto Baseline
Sweep.").
As long as the Reset input of U603B is held LO, the Q
output at U603B pin 9 stays LO. The LO is applied to one
of the inputs of all four AND-gates contained in Sweep
Logic Gate U620, and output pins 6 and 8 of U620 will be
held HI. As previously described, a HI on U620 pin 6
resets the Miller Sweep Generator.
When the timing capacitor is charged up to the reset
threshold of U640B, the holdoff time elapses, and U640B
switches back to the stable state to place a HI on the Q
output (pin 9). The End-of-Sweep Comparator output
on U607C previously became HI when the Miller Sweep
Generator finished resetting. With both inputs of U607C
now HI, the output on pin 8 is LO. This LO is inverted
to a HI by U607B and applied to both U603A and U603B
to remove the reset condition. The Q output of U603B at
pin 9 will remain LO when the reset is removed, while the
Q output on U603A (pin 5) will depend on the state of the
Set input when the reset is removed.
If the Set input to U603A is HI when the reset is
removed, the Q output will be LO. However, if the Set
input is LO, the Q output on U603A will be HI prior to
the reset removal, and it will remain HI after the reset is
removed. If the Set input of U603A was HI when the reset
was removed, the triggering signal will make a negative
transistion to set U603A before U603B is clocked, since
U603B clocks only on positive transitions.
In either case (with the Set input either HI or LO when
the holdoff period ends), the Q output of U603A will be
HI as U603B is clocked by the first positive transition of
the trigger signal after holdoff ends. The HI output present
on the D input of U603B (pin 12) is then transferred to the
Q output (pin 9), where it is applied to one input of each
AND-gate contained in Sweep Logic Gate U620. Gating
of the Swp Gate signal through U620 is controlled by the
HORIZONTAL MODE switch and the Delay circuit.
AUTO BASELINE SWEEP. This feature causes an
automatic sweep to be generated after about 100 ms if
no trigger signals are received. Generation of the Auto
Baseline signal was discussed previously in this section. The
Auto Baseline signal is LO either when trigger signals are
being received or when the circuit is disabled by using
NORM triggering.
The Auto Baseline signal is applied to pin 1 of NAND-
gate U607A, while the Holdoff Gate signal is applied to
U607A pin 2. As long as the Auto Baseline signal remains
LO, the output of U607A on pin 3 will be HI and will not
affect the Set input of U603B. When the Auto Baseline
signal goes HI in the absence of triggers (using either AUTO
or TV FIELD triggering), the output of U607A is an
inverted Holdoff Gate signal.
During holdoff, the output of the Holdoff Gate is a LO
and places a reset on both U603A and U603B. The reset
causes the Q output of U603B to be LO. At the end of the
holdoff period, pin 2 of U607A goes HI, and the reset is
removed from U603A and U603B. With both pins 1 and 2
of U607A HI, the output on pin 3 goes LO, and U603B
becomes set. Pin 9 of U603B becomes HI, and if no delay
is used U620 pin 6 goes LO to initiate the Sweep. If the
instrument is set for a delay, U620 pin 6 will go LO to start
the sweep at the end of the delay time. As long as no trigger
signal is received, U603B will continue to free run in the
manner just described to produce a Swp Gate signal to
U620 at the end of each holdoff period.
X-Y DISPLAY. Switching the SEC/DIV switch to
the X-Y position applies a LO logic level to U640B pin 11
and U607C pin 10 via CR640 and to U607A pin 1 via
CR610. The LO applied to U640B pin 11 prevents the
Holdoff monostable multivibrator from being triggered.
The LO applied to U607C pin 10 and to U607A pin 1
ensures that both U603A and U603B are held in the reset
condition and do not respond to input trigger signals.
ALT SYNC PULSE. A shaping network connected to
U640B pin 9 converts the leading edge of the negative-going
holdoff transitions into a narrow pulse suitable for use as
a synchronization signal. Zener diode VR644 holds the
voltage at one end of C644 at about 3 V, while the Q
output of U640B at pin 9 is HI. When the Q output of
U640B goes LO at the start of the holdoff period, C644
couples the negative-going edge of the pulse to the A lt Sync
signal line.
@ 3-17
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