Tektronix 2213 - Page 35

Th eory
of
O p
eration-2213 Service
W it h C H 1
E nable ΗΙ , gate dio d es C R 187 an d C R 177
are r everse b iased (see
F igure 3-3) . Series gate d io d es
CR 188 a nd C R 178
are forwar d biased, and t h e C h annel 1
vertical signal is
allowed to p ass to t h e Delay L ine Driver
.
Α L O CH 2
E
na b le
signal
app
lied to t h e C h annel 2 gate
d io d es forwar d biases C
R
287
an d CR277, an d t h e C
h an-
nel 2 vertical-signal
curre n t is s h unte d away from series
diod es CR 288 an d C R 278 . T
he
C
h annel 2 series d io d es a r e
reverse b iased, and t
h
e C
h annel 2 signal c u rrent is p revente d
from reac h i n g the Delay L
ine Driver .
C H A
NNEL 2 DIS PL AY O NL Y . Wh en C H 2 VER TICA L
M OD E is
selected, t h e
C
H 1 E nable signal goes L O an d t
h
e
CH 2
E nable signal goes ΗΙ . T h e C h annel 1
signal is
bloc
k ed, an d t he C ha n nel 2 sig n al reac
h
es
t h e Delay L ine
Driver .
ADD DIS PL AY
.
B
ot h Diode Gates are biased on to p ass
t
h
e C
h annel 1 an d Ch annel 2 vertical
sig n
als . T
he ch annel
signal curre n ts are summe d at t
h e inp u t to t h e Delay L ine
Driver . T he A dd
E nable signal su pp lies t he extra cu rrent
re q uire d to k ee p bot
h
Diode
Gates forwar d b iase d and to
maintain t h e proper d o
level at t h e b ase of t h e Delay L ine
Driver in p ut tra
n sistors (Q331 an d Q341) .
3- 8
F ig u re 3-3 . Diode gate b iasi
n g fo r α C h a nn el 1 display .
A LT ERNAT E A N D CH O PPED DIS PL AY
. The Dio d e
Gates
are switc h e d on and off by t
he
C
han nel E nab le
signals f r om t h e C h annel Switc
h ing L ogic circuit . Wh en
A L T VER TICA L M OD
E is selecte d , t h e Diode Gates
are switc hed at t
h
e
end of eac h trace . F or C H O P
VER TICA L M OD E , t h
e gates are switc hed at α rate of
abou t 250 kH z .
Χ - Υ DIS PL AY
. Setting t h e SEC/DI V switc h to t
h
e
Χ - Υ p osition activates
t he Χ - Υ d is p lay feat u re . T he C h annel
1 Dio d e Gate is h el d off,
and
t
h
e C
h annel
2
Dio d e Gate is
b iased on . T he C h annel 2
signal is p asse d to t he Delay L ine
Driver and u ltimately to t
h e
crt
to provi d e t h e Υ -Axis
dis p lay d eflection . T he X-Axis d
eflection signal is su pp lie d
to t he ΧΥAm p lifier (Diagram 7)
from t h e
C
h annel 1 signal
via t h e Internal Trigger
Amplifier (Diagram 4) .
Delay L ine Driver
T h e Delay L
ine Driver con verts t he signal current from
t he Dio d
e Gates into α signal voltage for a pp lication to t
h
e
Delay L
ine . T he Delay L ine Driver is configure d as
α
d ifferential s hunt fee dback am p lifier and is
com p ose d of
Q331,Q335,Q341, a
n
d Q345 .
In p ut cu rrents to common-
FR
O
M
C HA NNEL
SW I TCHING
L OG I
C
ADD
ENA BLE
VER T I CAL S IGN A L
TO D EL
AY L I NE
D RI VER
S IGNA L PATH
$ REVER SE BI
AS E D
DIODE
3826-25