Tektronix 2213 - Page 36

emitter transisto r s Q331 a nd Q341
are converted to
voltages
at th e basesof Q335
and Q345 respectively .
E mitter-followero utp ut
transistors Q335 an d Q345 t
h
e
n
drive t h e Delay L
ine
t
h roug h reverse termi n ations R 335-
C335 an d R 345-C345
. Am p lifier com p ensation is p
rovi ded
by R 340 an
d C340, an d sh unt fee d bac k is
s u p
p
lie d b y
R 336
a n
d
R 345 .
Delay L ine
Delay L
ine D
L
350 p rovi d es a b out 100 ns of
delay in
t he vertical
signal . Wh en using inter n al triggering (C H 1,
CH 2, or VER T M OD E ), t
h
e
delay time allows t h e Swee p
Generator sufficient time to
pro d uce α swee p before t h e
vertical signal reaches t he crt
d eflection p lates . T h is feature
permits viewing t he lea d ing
e dge of t he internal signal
t h at originates t he trigger p
ulse .
V ertical Out p ut Am
p lifier
T he V ertical
Output Amplifier, also s
h
ow
n
on
Diagram 3,
provi
d
es
final am p lification of t
h
e
in pu t signals for app li-
cation
to t h e d eflection p lates of
t he crt . Signals from the
Delay L i n e are a pp lie d to
α d iffere n tial amplifier in put
stage com p ose d of Q350 an
d Q360 . T he Delay L
ine is
terminate d in t
he p ro p er im p edanceby resistors R338
an d
R348 .
Resistor R355 sets t h e gain of Q350
and Q360 .
T
h ermal com p ensation of t
h
e stage
gain is p rovi de d by
t
h ermisto r R T356, connecte d in
series with R356 across
R355
. T he RC networ k s connecte
d across R355 p rovide
bot h low- and h ig h -frequency
com p ensation of t h e stage .
T he d iffere n tial out put
is a pp lie d to output transistor
p airs Q376-Q377 an d Q386-Q387 . T
h ese transistors form α
common-emitter s h unt-fee d bac
k am p lifier stage, wit h
R 376, R377, R386, and R387
serving as fee d bac k eleme n ts .
Capacitors C377 and C387,
co n necte d across R377 and
R387 respectively, p rovi d e
increasing negative fee d back
as t h e signal fre q uency rises
to limit t h e amplifier band-
wi d t h at t he up p er fre q uency
limit . Out pu t voltage from
t
he amplifier is d ivided b etween t he two
transistors of eac h
h alf . T he signal voltage applie d to t
h
e crt
vertical deflection
p lates is t h e sum of voltage drops
across t h e p airs (Q376-
Q377
and Q386-Q387) . T h e deflection
voltage is p ro-
p ortional to t he sig n al current d
riving t he bases of 0376
a n d Q386 .
BEAM F I N D switc
h
S390
(Diagram 6) normally s u pp lies
-8 .6 V directly to R390
to set t h e stage bias . Wh en t h e
BEAM F I ND butto
n
is p
resse d in and h el d , t he d irect
voltage is
remove
d
an
d t
h e
-8 .6-V
bias is p rovi ded via
series resistor R391 . T
h e output voltage swing is t
h
ereby
re duce d to
hold t h e vertical trace d eflectio n to
with i n t h e
graticule area .
C h annel Switc h ing L ogic
Circuit
T h eory of Operatio n -2213 Service
T h e C h
annel Switc h ing L ogic circuitry compose
d of
U 310A an
d U 317A selects eith er C
h
an
nel
1 or C
h annel2
an
d vario us d is p lay mo d es for crt dis p lay
via fro n t-panel
switc
h
es
an d th e Χ - Υ position of t
h
e S
E
C/DI
V switc h .
Wh en the
instrument is not i n the Χ - Υ M ode, signal
line ΧΥ is
grou nde d t h roug h contacts on t he SE C/DI V
switc h (Diagram 8) .
T h is actio n esta b lis h es L O logic
levels
on p ins C, Β ,
an d G of front-panel switc h S317 (C H 1-
BOTH-CH 2)
a nd on pins C a n d Β of S305 (I NT) .
Switc h S317
selects t he ve r tical ch a n nel signal
t h
at
d rives t he Delay
Line Driver via t h e C h ann el Diode
Gates .
Wit h S317 set to CH
1, α L O is ap p lie d to t he Set in
p
ut
( p in 4) of U 317A .
F li p -flo p U 317A will t h en be set, and
t he Q output ( p
in 5) will be ΗΙ . P in 5 of U 317A is t h e CH 1
En able signal
line, and w h en it is ΗΙ , t he C hannel 1 vertical
signal is gated to
t h e Delay L ine Driver . Wh en S317 is set
to C H 2, t
h
e
Reset in pu t of U 317A ( p in 1) will b e
h
el d L O
t h roug h C R 705 . T
he
C
H 2 E nable signal ( U 317A, p in 5) is
t hen set Η Ι and t
h e
C
hannel 2 vertical sig n al is gated to t
h
e
Delay L ine Driver
.
Setting S317 to t he BOTH p osition
removes t h e L O
from both t h e Set and
Reset inputs of U 317A . T h is action
allows t h e c
hannel selected for d is p lay to be determine d
eit
h
er by
t he logic level a pp lie d to t he D in pu t ( p in 2) and
t h
e clock
ap
plied to pin 3 or by t he logic level a pp lie d to
t
h
e
Set
a
nd R eset i np uts from t h e ADD-A L T-C H O
P switc h .
T
he ADD-A L T-C HO P switch (S315)
is enabled by t h e
L O
place d on pi n s Α , C, and
F w h en t h e CH 1-BOTH-CH 2
switch is set to BOTH . Wh
en
in ADD, S315
h ol d s bot h t he
Set an d R eset input of U 317A L O
t h ro u g h C R706 an d
C R 701 res p ectively
.
T
he Q an d Q out p uts of U 317A
will
t hen b e ΗΙ , and
bot h Ch annel 1 and C hannel 2 vertical
signals are gate d to t
he Delay L ine Driver . T h e sig n al
cur r ent is summe
d
at
t he input to t h e Delay L ine
Drive r ,
and t h e resulting
oscilloscope A dd vertical dis p lay is t
he
algebraic sum of t
h e two vertical signals .
T he Add E nable
circuit, com pose d of Q316, U 197C,
an d U 315A, is
activate d w hen both Dio d e Gates are turned
on for an A
dd vertical d isplay . Wit h t he Q an d Q out p
u
ts
of U 317A
ΗΙ , t he ou t p u t of U 315A will be L O and
tran-
sistor Q316 is biased on . T he collector of Q316
rises towar d
+5 V an d U 197C
is b iase d on . Transistor U197C supplies
t he additional
current re qu ired to k eep bot h Dio d e Gates
fo r war d biase
d an d to su pp ly t h e p ro p er do level to
t he
Delay L ine
Driver input . By p ass cap acitor C316
prevents
switch
ing transients from being introduced into t
h
e
Delay
L
ine Driver by t h e A dd E nable ci r cuit .
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