Tektronix 2213 - Page 37

T h eory of O p
eratio n -2213
Se
r vice
Wh en S315 is set to A LT, α ΗΙ is place d on both t h
e
Set
a nd R eset
inputs
of U 317A .
F li p -flo p U 317A will transfe r
t h e logic level on
t h e
D
in pu t (pin 2) to t he Q out p ut
( p in 5) on eac
h
cloc
k -pulse rising e dge . P in 1 of N A N D-gate
U 310A is
h
el d
Η
Ι
by t he
C
h op Oscillator out pu t, a nd p in 2
follows
t he Alt
Sync
sig n al p rod uce d b y t he H oldoff
circuit
r y in t he Α Sweep Generator (Diagram 5) . T
h e
o u t put of U 310A
( p in
3)
is t h erefore an inverte d Alt Sy nc
p ulse
. T h e signal on the D in put of U 317A ( p in 2)
follows
t h e logic level set by t h e Q out p u t p i n . As eac
h
cloc
k pu lse
occurs, t he states of t h e Q a nd Q
outputs reverse (toggle),
enabli ng C
h
a
n nel
1 an
d
C
hannel 2 Dio de Gates alter n ately
wit
h
eac
h sweep .
CHO P OSCILL ATO R .
Setti ng S315 to CH O P enables
t
h
e C
h op Oscillator and t h e C h op B lan k i ng circuit . P ins C
an d D of S315 are connecte d to p lace α L O
logic level
on
t h e Set in pu t (pin 10) of U 317 B . T h
e
Q
o u
t
p
ut of U 317 B
is
set ΗΙ and t h e C h op Oscillator is allowed to
r u n .
Α
ΗΙ
level is p resent on U 310D p
in
13
due to C308 b ei n g
c h arged to t h e ΗΙ level on U 310D
pi n 11 . Wh e n p in 12 of
U 310D also goes ΗΙ ,
t h e output of U 310D goes L O .
Ca p acitor C308 now
must d isc harge to t he new do level
.
As
soon as
t
he c ha r ge of C308 reac h es t h e L O t h res h ol d
level of U 310D,
t h e out p ut at pin 11 switches ΗΙ again and
C308 c
h
a
r ges towar d t h e ΗΙ logic level (see F igure 3-4) .
Wh en t
h
e ΗΙ
switch ing t h res h ol d level is reac hed , t h e
out pu t of U 301D
changes state to L O again . T h is cycle
continues at
about
500
kH z to pro du ce both t he C hop
Cloc
k
and t
he
C
h o p Bla nk signals .
T
h e
C
h o p signal is gated t h r o u g h N A N D-gate U 310C
a
n
d a pp
lied to U 310A p in 1 . T he Alt Sy nc p ulse on U 310A
pin
2
is ΗΙ (except during h ol doff time) so t h e out put of
U 310A p in 3 is t he inverte d C h o p Oscillator
sig n
al on
p in
1 .
T h is sig n al is a pp lie d to t he Cloc k In pu t ( p i n 3) of
U 317A to d r ive t h e C hannel Switc h i n g circuitry . Since fli
p
-
flo pU
317A cloc k s with rising ed ges only, t h e fre q uency of
t h e c h opp ed c
hannel switch ing is about 250 kH z .
T h e signal out p ut from U 310C p in 8 is also fed to t he
C
h op Blan k ing circ u it . Capacitor C311 and resistors R310
and R311
form α d ifferentiating circuit t h at pro d uces
p ositive and negative s
h
ort- du
ratio n pu lses w h en t he C h o p
Oscillator sig
n
al c
h anges levels .
T
h e do level at U 310 B p ins 4 an d 5 is set slig h tly above
t h
e
ΗΙ
switch ing t h res hold logic by α voltage divi d er con-
sisting of R310 an
d R311 . P ositive p ulses from C311 con-
tinue
to h ol d U310B above the t h res h ol d level, so t
he
output remains L O . N egative
pulses fromC311 drop below
3- 1 0
t he t h res h ol d
level
of U 310B ,
and t h e out put of U 310 B
switch es ΗΙ
for
α
d uration of ab out 0 .4 μ s (see F igure 3-4)
to p rod
u
ce
t h e p ositive C h o p B lan k ing pulse
.
T
he
C
hop
Blan
k ing pu lse is fe d to t h e Ζ -Axis Am
p lifier an d is used to
prevent d isplay of t h e t r ansistio
n
s w
hen switch i ng b etwee n
vertical ch ann els .
Internal Trigger Switch ing L ogic
internal trigger-selection
sig n als to the Trigger P ic koff
Amplifier (Diag r am 2) a
r e p ro d uce d i n α logic circ u it com-
pose d of U 305 B , U 305C,
U 305D,U 315 B , a nd U 315C .
T he T RIGG ER ΙΝΤ
Source
switc
h (S305), i n co nju nction
with C H 1-BOTH-CH 2 switc
h
(S317),
determi n
es
t h e
i n ternal trigge r sou r ce selected . Wh
en eit h er t he C H 1 o r
CH 2 Internal Trigge r
signal
is
selecte d by S305, t h e
selected c h a n nel
will
be
t he i n ter n al t r igger sou rce . Wh en
VER T
M
OD
E is selecte d as t he i n ter n al t r igger signal, t h e
p
ositio
n
of S317
determines t he cha nn el(s) selecte d as t h e
i n ternal trigger sou r ce .
CH ANNEL 1 SO UR C E . T he ΧΥ signal li ne fr om t he Α
S
E
C/DI V
switch (S630 B ) a p plies α L O logic level to ΙΝΤ
switc
h
S305 on
p ins Β an d C . In t he C H 1 p osition, t he
L O
is cou p le d from p in C to p in D an d app lie d to U 305B
pin 4 .
T he L O is gate d t h roug h U305B a nd app lied to t he CH 1
Trig sig n al line i n α wired -A N D connection . T he L O from
U
305B
is a pp lie d to Q273 i n t h e C h a n nel 2 Internal Trigger
P ic k off Amplifier (Diagram 2) to bias it off, t hu s preventing
the
C
ha n nel 2 signal from being selecte d . Operation of t he
Internal Trigger P ic koff Am p lifiers is disc u sse d in t he
"C hann el 1 and C h annel 2 P reamps" circuit d escri p tions .
Concurrently, p
ins
9 and 10 of U 305C
are pu lle d ΗΙ
th ro ug
h
R304
an d
R300
respectively to place α ΗΙ at
U305C p
in
8 .
T he ΗΙ fro m U 305C to t h e wired -A ND
connection on t h e C H 2 Trig sig n al li n e en a b les t he out put
of U 315B to control t h e logic level of t
h
e CH 2 Trig
signal .
Control is accom p lis hed by t he logic levels on t h e in
p
u ts of
U 305D, pins 12an d 13 .
T he L O on U 305B pin 4 ( p laced t h ere by S305) also
occurs on U 305D p in 13 . T h is ensures α L O at U 305D
p in 11, w h ic h is a pp lie d to U 315C pin 9 and to U315 B
pin 5 . T h e logic l evel app lied to U 315C pin 9
h
as no effect
on t he C H 1 Trig signal b ecause α L O is alrea
d y p resent
at
t he wired -A ND connection to t
he signal line .
H
owever, t he
L O app lie d to U315 B pin 5 ensures t
h
at t
h
e out p
u
t
of
U315B is ΗΙ . Wh en t h e CH 2 Trig signal is ΗΙ , Q173 i
n
t
h
e
C
hann el 1 Internal Trigger P ic koff Am p lifier is biase d on
an d t h e C hannel 1 signal is p asse d to t
h
e Internal
Trigger
Amplifie r (Diagram 4) .