Tektronix 2213 - Page 44

an d α
voltage d
ivider com p ose d of R645 and R 646 establish
t he charging
voltage
of
hol
d
off timing
ca p acitors C645,
C646,
an d
C647
. The capacitor (or combination of
capacitors) used is switche d into the hol d off circuit by
contacts on S630B, the SEC/DIV timing switch .
During h
ol
d off
time,
while
U 640B p in 9 remains L O,
the output
of U 607C
will
b
e
ΗΙ .
Inverter
U 607B will invert
the ΗΙ to α L O logic level that is then applied to the R eset
inputs of both U603A an d U 603B at p ins 1 an d 13 respec-
tively . The L O at these inputs hol d s both flip-flops in t he
r
eset state, with t he Q outp uts ΗΙ and Q outputs L O . In
the
reset state, flip-flops U 603A and U603B will not
r es p ond to input trigger signals . The Set input of U 603B is
hel d ΗΙ
by
the
output of U 607A an d d oes n ot affect flip-
flop operation . (With
A UTO trigger mode selected, α
different condition at the Set input of U 603B occurs when
triggering signals are not received ; see "Auto Baseline
Sweep .") .
As
long
as
the R eset input of U 603B is h eld LO, the Q
output at U
603B
pin
9
stays L
O .
The L O is ap p lied to one
of the inputs of all four AND-gates contained i n Sweep
Logic Gate U 620, and output pins 6 and 8 of U 620 will be
held ΗΙ . As p reviously describe d , α ΗΙ on U 620 pin 6
r esets the M iller Sweep Generator .
When the timing capacitor is charged
up
to
the
reset
threshold of U 640B, the
h
ol d
off time
elapses, an d U 640B
switches b
ack
to the stable state to p lace α ΗΙ on the
Q
output (pin 9) . The End-of-Sweep Comparator output
on U 607C p
reviously
b ecame ΗΙ
when t he M iller Sweep
Generator finished resetting . W ith both i np uts of U 607C
now ΗΙ , the output on
p
in 8 is L O . This L O is inverted
to
α
ΗΙ by U
607B an
d
app
lie d to both
U603A
and
U603 B
to remove the reset condition
.
The Q output of U 603B at
p in 9 will remain L O when the r eset is r emoved, while the
Q output
on U 603A ( p in 5) will d epend on the state of the
Set
input when the reset
is removed .
If the Set input to U 603A is ΗΙ
when
the reset is
remove d , the Q outp ut will b e L O . H owever, if the Set
input is LO, the Q output on U 603A will b e ΗΙ prior to
the reset r emoval,
an
d
it
will
remain ΗΙ after the reset is
r emove d . If the Set in p ut of
U 603A was ΗΙ
when
the reset
was removed, the triggering signal will make α n egative
transistion to set U 603A b efore U 603B is clocke d , since
U 603B clocks only on positive transitions .
In either case (with t he Set input either ΗΙ or LO when
the h oldoff p erio d end s), the Q output of U 603A will b e
ΗΙ as U 603B is clocked b y the first positive transition of
the trigger signal after holdoff ends . The ΗΙ output present
on the D input of U 603B (pin 12) is then transferre d to the
Q output (pin
9),
where
it is app lied to one input of each
Theory of O p eration-2213 Service
A ND-gate containe d i n Sweep Logic Gate U 620 . Gating
of the Swp Gate signal through U620 is controlled b y the
H ORIZONTAL MODE switch and the Delay circuit .
A UTO B ASELINE SW EEP . This feature causes
an
automatic sweep to b e generated after about 100 ms if
no trigger signals are r eceived . Generation of the Auto
B
aseline signal was d iscussed p reviously in t his section . The
Auto
B
aseline signal is L O either when trigger signals are
b eing received or when t he circuit is d isabled by u sing
N ORM triggering .
The Auto Baseline signal is app lied to pin
1
of
N AND-
gate
U
607A,
while the H ol d off Gate signal
is applie d to
U
607A
pin
2 .
As long as the Auto Baseline signal
remains
L O, the output of U 607A
on
pin
3
will
be ΗΙ and
will
not
affect the Set input of U 603B . When t he Auto Baseline
signal goes Η Ι in the absence of triggers (using either
AUTO
or
TV
FIELD triggering), the
output
of
U 607A is an
inverte d H oldoff Gate signal .
During h ol d off, the output of the H oldoff Gate is α L O
and places α r eset on both U603A and U603B . The reset
causes the Q outp ut of U 603B to b e L O . At the end of the
h
oldoff p erio d , p
in
2 of U 607A goes ΗΙ , and the r eset is
removed from U 603A an d U
603B . W
ith
both pins 1 an d 2
of U 607A ΗΙ , the output on p in 3 goes
L O, an d U 603B
becomes set . P in 9 of U 603B becomes ΗΙ , and if
no
delay
is used U620 pin 6 goes L O to initiate the Sweep .
If
the
instrument is set for α delay, U 620 p in 6 will go L
O
to start
the sweep at the end of the d elay time . As long as no trigger
signal
is
received, U
603B
will
continue to free run in the
manner just d escribed to p
roduce α Swp Gate signal to
U
620 at
the end of each holdoff p
erio d
.
Χ - Υ DISPLAY . Switching the SEC/DIV switch to
the Χ - Υ p osition applies α L O logic level to U 640B pin 11
and U607C pin 10 via CR640 an d to U 607A p in 1 via
CR610 . The L O applie d
to
U 640B pin 11 prevents the
H oldoff monostable multivibrator from b eing triggere d .
The L O app lied to U 607C pin 10 and to U 607A pin 1
ensures that both U603A and U603B are h eld i n t he r eset
con d ition an d d o n ot respon d to input trigger signals .
A
LT SYNC PULSE . Α s haping network connected to
U
640B
pin
9
converts the lea d ing edge of the negative-going
h oldoff transitions into α narrow pulse suitable for use as
α
synchronization signal . Zener diode VR644 h ol d s the
voltage at
one end of
C644 at
about
3
V, while the Q
outp ut of U 640B at pin 9 is ΗΙ . When the Q output of
U 640B goes L O at the start of the h ol d off p erio d , C644
couples the n egative-going e d ge of the pulse to the Alt Sync
signal line .
3- 1
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