Tektronix 2213 - Page 45

T heo r y of O p eratio n -2213 Se r vice
Cap
acitor
C644 c
h arges
ra p idly to
t he new voltage
d iffere n ce t h roug
h
R 642 to p ro duce α
very
narrow pulse
o
u t p
ut
across
R642 .
Wh en t he h ol d off pe r io d en
ds,
t h e
Q
ou
tput
of
U 640 B goes ΗΙ again a
n
d C644 c
h
ar ges
i n t h
e
op
posite
direction
t
hr
o
ug
h VR 644
. T h e resulting
Alt Sy
n
c
signal is applie
d to the
C
h
an
n el Switc h ing circuit to sy n -
ch ro n ize the horizontal d is p lay wit h c h annel switc h ing
tra n sitio n s w hen using A
L
T VER TICA L M OD E .
Delay Circuit
T h e Delay ci r c u it, com p ose d of Q624, Q632, Q644,
Q650,Q652, U 607D, a nd associated com pon e n ts, ge ne r ates
t he timing and gate sig n als r eq uire d to p ro d uce t
h
e inte n -
sifie
d
Swee p dis p lay a
n
d to
provi d
e
t he
va r ia
b
le
Sweep
d elay . H O R IZO N TA L M OD E switc h 5650 controls t h e
display
mo
d
e
( ΝΟ IDLY, I N T EN S,
or
DL Y'D), and D EL AY
TIME switc h S660 selects t he b asic d elay time (0 .2 ms,
10 μ s, or 0 .5 μ s) . T h e D EL AY TIME MUL TI PL I ER
con trol ( R 658) increases t he possi b le d elay availa b le by up
to at least twe n ty times
t
h e basic d elay .
ΝΟ D L Y . W it h H O R IZO N TA L M
OD
E switc h
S650
set
to t he ΝΟ D L Y p osition, t h e Delay circ u it is d isabled and
the Sweep starts imme d iately after t he Swp Gate sig n al is
produced by U 603 B at p i n 9 .
P
in D of S650 is op en, so p i n s
4
a
nd 10 of U 620
are
pu lle d ΗΙ t
h ro
u
g
h R 608 . Wh en t he
Sw
p Gate occu rs, p i n s 1, 2, 5,
an
d 9
of
U
620 all
go ΗΙ .
T
h e
ΗΙ on
pin 5 is
A
N De d with t he
ΗΙ on
pin 4, and U 620
pi n
6 goes
L
O
to i n itiate α Sweep . T h e o utpu t of t he Delay
circuit
is
d isa b le d b y groun ding t he b ase o f Q644 t h roug h
p in Α of S650 . T
h
is action
h
ol
d
s t
h e
Dly Gate sig
n
al at t
h e
collector
of
Q652 at
α
ΗΙ
logic level .
W
it h
t
h
e Dly
Gate
signal
ΗΙ ,
α
ΗΙ
is also gate d t hr o
ug
h U
620
to p in
8 to
b ias
off
C R 620 .
Diod e
C R 622 is
t hen forward
b iase d to enable
t
he I n tens L evel cu rrent from R
622
to t he Ζ
-D
r ive line to
unb la nk t he c r t fo r t h e Swee p d isplay .
I N T EN S . W it h 5650 set to t h e I N T EN S p osition, t he
Delay circ u it is enable d . Νο delay in t he Swee p occu rs in
t h is mo d e, bu t an
i
n tensifie d zone is d is p laye d . T he amo un t
of d elay b
etween
t
he start
of t
he Sweep a
nd t h
e
start of
the intensifie d zone is dete r mine
d
b y
t
h
e D EL AY TIME
switc h setti ng an d t he MUL TI PL I ER co n t r ol p osition
.
T h e inte n sifie d zo ne is generated by gati ng t h roug h
U 607D to control t he
Ζ
-Axis gating dio d es, C R 619 and
C R 621 (see F igure 3-6) . P i n 12 of U 607D is p ulle d ΗΙ
t h roug h R 607 as p i n Η of S650 is op en . Wh en t he d elay
time h as e la p se d , U 607D pi n 13 is also switc he d ΗΙ (by t h e
Dly Gate signal), and p i n 11 goes L O . Dio d e CR 619
b ecomes reverse b iase d , and C R 621 p asses t he I n te n s L evel
curre
n
t to the Ζ -D r ive li ne . T he ext r a c u rr ent is a d d e d to
FR O M
HO RI ZO N TA L
M OD E SW I TC H
PIN D
HO R I ZO N TA L
M OD E SW I TC H
PIN Η
S WP DU TY

_
TO
A
U TO
I
N TEN
S I
TY
CR 622
3827-16
3-18
Fig u re 3-6 . Sim
p lifie d d iag r
am
of t h
e
Ζ -Axis
Switc h i
n g
L ogic
circ u
it .