List of Figures
1-1 Multiple ePWM Modules ................................................................................................... 15
1-2 Submodules and Signal Connections for an ePWM Module ......................................................... 16
1-3 ePWM Submodules and Critical Internal Signal Interconnects ...................................................... 17
2-1 Time-Base Submodule Block Diagram .................................................................................. 23
2-2 Time-Base Submodule Signals and Registers ......................................................................... 24
2-3 Time-Base Frequency and Period ....................................................................................... 26
2-4 Time-Base Counter Synchronization Scheme 1 ....................................................................... 27
2-5 Time-Base Counter Synchronization Scheme 2 ....................................................................... 28
2-6 Time-Base Counter Synchronization Scheme 3 ....................................................................... 29
2-7 Time-Base Up-Count Mode Waveforms ................................................................................ 30
2-8 Time-Base Down-Count Mode Waveforms ............................................................................. 31
2-9 Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event ...... 31
2-10 Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event ......... 32
2-11 Counter-Compare Submodule ............................................................................................ 32
2-12 Detailed View of the Counter-Compare Submodule ................................................................... 33
2-13 Counter-Compare Event Waveforms in Up-Count Mode ............................................................. 35
2-14 Counter-Compare Events in Down-Count Mode ....................................................................... 35
2-15 Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down On
Synchronization Event .................................................................................................... 36
2-16 Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization
Event ........................................................................................................................ 36
2-17 Action-Qualifier Submodule ............................................................................................... 37
2-18 Action-Qualifier Submodule Inputs and Outputs ....................................................................... 38
2-19 Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ............................................ 39
2-20 Up-Down-Count Mode Symmetrical Waveform ........................................................................ 42
2-21 Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB—Active High .................................................................................................... 43
2-22 Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxB—Active Low .................................................................................................... 44
2-23 Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA .............. 45
2-24 Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Active Low ................................................................................................... 47
2-25 Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB — Complementary ............................................................................................. 48
2-26 Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxA—Active
Low ........................................................................................................................... 49
2-27 Dead_Band Submodule ................................................................................................... 50
2-28 Configuration Options for the Dead-Band Submodule ................................................................ 51
2-29 Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ..................................................... 53
2-30 PWM-Chopper Submodule ............................................................................................... 55
2-31 PWM-Chopper Submodule Operational Details ........................................................................ 56
2-32 Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only .................................. 56
2-33 PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ......... 57
2-34 PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses ........................................................................................................................ 58
2-35 Trip-Zone Submodule ...................................................................................................... 59
2-36 Trip-Zone Submodule Mode Control Logic ............................................................................. 62
2-37 Trip-Zone Submodule Interrupt Logic.................................................................................... 63
2-38 Event-Trigger Submodule ................................................................................................. 63
2-39 Event-Trigger Submodule Inter-Connectivity of ADC Start of Conversion and Interrupt Signals ................ 64
2-40 Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs .......................................... 65
2-41 Event-Trigger Interrupt Generator ........................................................................................ 66
2-42 Event-Trigger SOCA Pulse Generator .................................................................................. 67
SPRU791D – November 2004 – Revised October 2007 List of Figures 5
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