Texas Instruments 28xxx

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Dead-Band Generator (DB) Submodule
The dead-band submodule supports independent values for rising-edge (RED) and falling-edge (FED)
delays. The amount of delay is programmed using the DBRED and DBFED registers. These are 10-bit
registers and their value represents the number of time-base clock, TBCLK, periods a signal edge is
delayed by. For example, the formula to calculate falling-edge-delay and rising-edge-delay are:
FED = DBFED × T
TBCLK
RED = DBRED × T
TBCLK
Where T
TBCLK
is the period of TBCLK, the prescaled version of SYSCLKOUT.
For convenience, delay values for various TBCLK options are shown in Table 2-14 .
Table 2-14. Dead-Band Delay Values in μ S as a Function of DBFED and DBRED
Dead-Band Value Dead-Band Delay in μ S
(1)
DBFED, DBRED TBCLK = SYSCLKOUT/1 TBCLK = SYSCLKOUT /2 TBCLK = SYSCLKOUT/4
1 0.01 μ S 0.02 μ S 0.04 μ S
5 0.05 μ S 0.10 μ S 0.20 μ S
10 0.10 μ S 0.20 μ S 0.40 μ S
100 1.00 μ S 2.00 μ S 4.00 μ S
200 2.00 μ S 4.00 μ S 8.00 μ S
300 3.00 μ S 6.00 μ S 12.00 μ S
400 4.00 μ S 8.00 μ S 16.00 μ S
500 5.00 μ S 10.00 μ S 20.00 μ S
600 6.00 μ S 12.00 μ S 24.00 μ S
700 7.00 μ S 14.00 μ S 28.00 μ S
800 8.00 μ S 16.00 μ S 32.00 μ S
900 9.00 μ S 18.00 μ S 36.00 μ S
1000 10.00 μ S 20.00 μ S 40.00 μ S
(1)
Table values are calculated based on SYSCLKOUT = 100 MHz.
54 ePWM Submodules SPRU791D – November 2004 – Revised October 2007
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