4.2 Counter-Compare Submodule Registers
Counter-Compare Submodule Registers
Figure 4-5. Time-Base Status Register (TBSTS)
15 8
Reserved
R-0
7 3 2 1 0
Reserved CTRMAX SYNCI CTRDIR
R-0 R/W1C-0 R/W1C-0 R-1
LEGEND: R/W = Read/Write; R = Read only; R/W1C = Read/Write 1 to clear; -n = value after reset
Table 4-5. Time-Base Status Register (TBSTS) Field Descriptions
Bit Field Value Description
15:3 Reserved Reserved
2 CTRMAX Time-Base Counter Max Latched Status Bit
0 Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will
have no effect.
1 Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing
a 1 to this bit will clear the latched event.
1 SYNCI Input Synchronization Latched Status Bit
0 Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has
occurred.
1 Reading a 1 on this bit indicates that an external synchronization event has occurred
(EPWMxSYNCI). Writing a 1 to this bit will clear the latched event.
0 CTRDIR Time-Base Counter Direction Status Bit. At reset, the counter is frozen; therefore, this bit has no
meaning. To make this bit meaningful, you must first set the appropriate mode via
TBCTL[CTRMODE].
0 Time-Base Counter is currently counting down.
1 Time-Base Counter is currently counting up.
Figure 4-6 through Figure 4-8 and Table 4-6 through Table 4-8 illustrate the counter-compare submodule
control and status registers.
Figure 4-6. Counter-Compare A Register (CMPA)
15 0
CMPA
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRU791D – November 2004 – Revised October 2007 Registers 97
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