~----9_4_5_42_4_-9_1_0_1
________________________________________________
__
The character
counter
and character address
counter
share hardware circuitry. The 12-bit
character address
counter
(KAD, 11-0) consists
of
three hexadecimal
counter
stages. The carry
from the first stage, KCOL, feeds the second stage and the single-stage character counter.
The character address
counter
is
a 12-bit
counter
that
contains the character address
that
is
presented
to
the cursor address comparator, refresh memory, the character decoder ROM, and
the row decoder ROM. The address in the
counter
is
compared
to
the cursor address. When the
two addresses are identical, the
next
character
is
fetched from memory for screen refresh at
the
current cursor location and displayed in reverse video (inside the cursor).
The timer control ROMs (character decoder ROM, row decoder ROM, and sync decoder ROM)
decode
the
output
of
the character address
counter
to
determine the instantaneous position
along a TV scan line (from character time 0 through
99)
and
the
position
of
the scan line in
the
raster. The row decode
of
the most significant bits determines
whether
the row
is
in
the
display
region
or
whether
it
occurs during vertical retrace (blanking and sync). The row decoder
information, along with line decode and character position along a scan line, determines
the
instant at which events such
as
horizontal sync, horizontal blanking, vertical sync, and vertical
blanking occur.
The character address
counter
starts counting
at
000
16
• The
counter
is initialized
to
000
16
after
completing a scan
of
a frame (one noninterlaced sweep
of
the
display screen). A frame
is
repeated
50
or
60 times per second and
the
same frequency
as
the
input ac power. A SO-hertz
rate requires
that
314
lines are scanned, while 262 lines are scanned for a 60-hertz rate. The
horizontal scan frequency
is
15.
720
kilohertz for
both
SO-hertz and 60-hertz frame rates.
The character address
counter
divides a scan line
into
100 equal segments (character times) - 80
char?cter times for display
of
80
characters and 20 character times for horizontal blanking and
synchronization. The
counter
must also have incremented
only
80 character times at the
beginning
of
the
next
row
of
characters.
As
an example, consider
the
following illustration
of
the
character address counts for the first and second display rows:
CHARACTER
0
OF
LINE
CHARACTER
79
CHARACTER
99
04F
16
1-
------
063161
0
50
1
6
- - - - - - - - -
09
F
1
6
- - - - -
-0
83
1 6
000
ROW
1
ROW
2
\
------•'
\ I
.__
_____________
v v
DISPLAY
AREA
HORIZONTAL
(A)
i
36303
BLANK!
NG
AND
SYNC
During the scan
of
the first row, the
count
progresses from
000
16
(0
10
)
to
063
16
(99
10
).
But,
since only 80 characters are displayed, the first character
of
the second row must be read from
memory location
050
16
(not
064
16
).
The value stored in the character address
counter
is
copied
into
the
character address latch
at
character time 0 (enabled by
KOOL)
of
each scan line (only
the
most significant eight bits are
latched). Figures
1-5
2 and 1-53 show
that
the values are
00, 05,
OA,
etc. The value in
the
character address latch
is
written back
into
the
character address
counter
at character time 99
(enabled by K99L) (the least significant four bits are cleared). This operation permits the
character address
counter
to
continuously
count
from an initial value,
i,
to
i + 63
16
(000-063
16
,
OA0-103
16
, etc.) for each scan line
of
a particular row.
For
the 960-character display, there are
1-66 Digital Systems Division
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