MAX-M10M-Integration manual
Baud rate Data bits Parity Stop bits
230400 8 none 1
460800 8 none 1
921600 8 none 1
Table 14: Possible UART interface configurations
Allow a short time delay of typically 100 ms between sending a baud rate change message and
providing input data at the new rate. Otherwise some input characters may be ignored or the port
could be disabled until the interface is able to process the new baud rate.
The default baud rate is 9600 baud. Using a lower baud rate may cause buffering problems.
If there is too much data for the interface's bandwidth, the output buffer will fill up. Once the buffer
space is exceeded, new messages to be sent will be dropped. To prevent message loss, the baud rate
and the number of enabled messages should be selected carefully.
3.2.2 I2C
An I2C interface is available for communication with an external host CPU in I2C Fast-mode.
Backwards compatibility with Standard-mode I2C bus operation is not supported. The interface can
be operated only in slave mode with a maximum bit rate of 400 kbit/s. The interface can make use
of clock stretching by holding the SCL line LOW to pause a transaction. In this case, the bit transfer
rate is reduced. The maximum clock stretching time is 20 ms.
The SCL and SDA pins have internal pull-up resistors which should be sufficient for most
applications. However, depending on the clock speed of the host and the capacitive load on the
I2C lines, additional external pull-up resistors may be necessary. The higher the speed and the
capacitance load, the lower the pull-up resistor needs to be.
To poll or set the I2C address, use the CFG-I2C-ADDRESS configuration item (see the u-blox M10
interface description [3]). The CFG-I2C-ADDRESS configuration item is an 8-bit value containing
the I2C address in the 7 most significant bits plus a 0 as the least significant bit. Thus, the default
address becomes 0x84(1000 0100).
In designs where the host uses the same I2C bus to communicate with more than one u-blox
receiver, each receiver's I2C address must be configured with a different value.
3.2.2.1 I2C register layout
As shown in Figure 6, there are 256 registers. The data registers 0 to 252, at addresses 0x00 to 0xFC,
contain reserved information and must not be used. Hence, only the last three registers are left for
communication. The registers 0xFD and 0xFE contain the currently available number of bytes to be
read, while the register 0xFF buffers the message stream. The 0xFF address delivers a 0xFF byte
value if there is no data awaiting for transmission, or all the bytes have been read.
UBX-22038241 - R02
3 Receiver functionality Page 23 of 92
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