SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26 Design-in
Page 141 of 217
If a 3.0 V application processor is used, then it is recommended to connect the 1.8 V auxiliary UART interface of
the module by means of appropriate unidirectional voltage translators using the module V_INT output as the
1.8 V supply for the voltage translators on the module side, as described in Figure 75.
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
GND
SARA-G3 series
(1.8V DCE)
29
TXD_AUX
28
RXD_AUX
GND
1V8
B1 A1
GND
U1
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR1
DIR2
OE
VCC
B2 A2
0 ohm
0 ohm
TP
TP
TP
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
GND
SARA-U2 series
(versions ‘04’ onwards)
(1.8V DCE)
26
SDA
27
SCL
GND
1V8
B1 A1
GND
U1
VCCBVCCA
Unidirectional
Voltage Translator
C1
C2
3V0
DIR1
DIR2
OE
VCC
B2 A2
0 ohm
0 ohm
TP
TP
TP
Figure 75: UART AUX interface application circuit connecting a 3.0 V application processor
Part Number - Manufacturer
100 nF Capacitor Ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
Unidirectional Voltage Translator
SN74AVC2T245
46
- Texas Instruments
Table 48: Component for UART AUX interface application circuit connecting a 3.0 V application processor
See the Firmware Update Application Note [27] for additional guidelines regarding the procedure for SARA-G3
modules’ firmware upgrade over the auxiliary UART interface using the u-blox EasyFlash tool.
Any external signal connected to the auxiliary UART interface must be tri-stated or set low when the
module is in power-down mode and during the module power-on sequence (at least until the activation
of the V_INT output), to avoid latch-up of circuits and allow a proper boot of the module. If the external
signals connected to the cellular module cannot be tri-stated or set low, insert a multi-channel digital
switch (e.g. TI SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set
to high impedance during module power down mode and during the module power-on sequence.
The ESD sensitivity rating of auxiliary UART pins is 1 kV (Human Body Model according to JESD22-A114).
A higher protection level could be required if the lines are externally accessible on the application board.
This higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) close to accessible points.
2.6.2.2 Guidelines for UART AUX layout design
The auxiliary UART serial interface requires the same consideration regarding electro-magnetic interference as
any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since
the signals can cause the radiation of some harmonics of the digital data frequency.
46
Voltage translator providing partial power down feature so that the DTE 3.0 V supply can be also ramped up before V_INT 1.8 V supply
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