SARA-R5 series - System integration manual
UBX-19041356 - R04 System description Page 35 of 118
C1-Public
When an OFF-to-ON transition occurs on the DTR input line, the UART is re-enabled and the module,
if it was in idle mode, switches from idle to active mode after ~15 ms: this is the UART and module
“wake-up time”.
If the DTR line is set to ON by the DTE, then the module is not allowed to enter the idle mode or
deep-sleep mode and the UART is kept enabled until the DTR line is set to OFF.
When the AT+UPSV=3 configuration is enabled, the DTR input line can still be used by the DTE to
control the module behavior according to AT&D command configuration (see the SARA-R5 series AT
commands manual [2]).
☞ The CTS output line indicates the UART power saving state as illustrated in Figure 18, if HW flow
control is enabled with AT+UPSV=3.
Wake-up via data reception
The UART wake-up via data reception consists of a special configuration during idle mode of the
module TXD input line that causes the system wake-up when an OFF-to-ON transition occurs on the
TXD input line. In particular, the UART is enabled and the module switches from the idle mode to active
mode within ~15 ms from the first character received: this is the system “wake-up time”.
As a consequence, the first character sent by the DTE when the UART is disabled (i.e. the wake-up
character) is not a valid communication character even if the wake-up via data reception configuration
is active, because it cannot be recognized, and the recognition of the subsequent characters is
guaranteed only after the complete system wake-up (i.e. after ~15 ms).
The UART wake-up via data reception configuration is active in the following case:
• AT+UPSV=1 or AT+UPSV=4 is set with hardware flow control disabled
The UART wake-up via data reception configuration is not active on the TXD input, and therefore all
the data sent by the DTE is lost, in the following cases:
• AT+UPSV=2 is set and the RTS line is set OFF
• AT+UPSV=3 is set and the DTR line is set OFF
Figure 19 and Figure 20 show examples of common scenarios and timing constraints:
• AT+UPSV=1 power saving configuration is active and the timeout from last data received to idle
mode start is set to 2000 GSM frames (AT+UPSV=1,2000)
• Hardware flow control is disabled
Figure 19 shows the case where the module UART is disabled and only a wake-up is forced. In this
scenario the only character sent by the DTE is the wake-up character; as a consequence, the DCE
module UART is disabled when the timeout from last data received expires (2000 GSM frames without
data reception, as the default case).
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