Ublox SARA-R5 Series - Schematic for SARA-R5 Series Module Integration

SARA-R5 series - System integration manual
UBX-19041356 - R04 Design-in Page 95 of 118
C1-Public
2.12 Schematic for SARA-R5 series module integration
Figure 71 is an example of a schematic diagram where a SARA-R5 series product is integrated into an
application board using most of the available interfaces and functions of the module.
3V8
GND
10uF 10nF
SARA-R5 series
52 VCC
53 VCC
51 VCC
68pF
RSVD2
18 RESET_N
Application
processor
Open
drain
output
15 PWR_ON
Open
drain
output
TP
TP
62
ANT_DET
10k
27pF
ESD
68nH
56
Connector
Cellular
antenna
33pF
ANT
29
USB_D+
28
USB_D-
17
VUSB_DET
Test-Point
Test-Point
Test-Point
39nH
15pF
15pF100nF
EXT_INT
33
3V8
Network
indicator
16
GPIO1
SDIO_D0
SDIO_D3
SDIO_D1
47
48
49
SDIO_D2
SDIO_CLK
44
45
36I2S_CLK
34I2S_WA
35I2S_TXD
37I2S_RXD
12
TXD
13
RXD
8
DCD
10
RTS
11
CTS
9
DTR
6
DSR
7
RI
TP
TP
TXD
RXD
DCD
RTS
CTS
DTR
DSR
RI
1.8 V DTE
GND GND
0Ω
0Ω
47pF
SIM CARD
HOLDER
VCC (C1)
VPP (C6)
IO (C7)
CLK (C3)
RST (C2)
GND (C5)
47pF 47pF 100nF
41VSIM
39SIM_IO
38SIM_CLK
40SIM_RST
47pF
SW1
SW2
4V_INT
42GPIO5
470k
ESD ESD ESD ESD ESD ESD
1k
TP
V_INT
ANT_GNSS
31
GNSS
antenna
24GPIO3
V_INT
B1 A1
B2 A2
VCCB VCCA
SN74AVC4T774
voltage translator
100nF
100nF
3V0
TXD1
4.7k
IN
OUT
LDO regulator
SHDN
4.7k
3V8 3V0
23GPIO2
V_INT
SDA_A
SDA_B
GND
SCL_A
SCL_B
VCCA
VCCB
TCA9406
I2C voltage translator
100nF
100nF
100nF
47k
SDA2
SCL2
VCC
DIR1/3
OE
GND
GPIO4 25
u-blox GNSS
3.0 V receiver
26SDA
27SCL
SARA-R500S / SARA-R510S modules only
GND
DIR2/4
OE
EXTINT
SDIO_CMD
46 B3 A3
B4 A4
TIMEPULSE
GND
3V8
Time
Pulse
19
GPIO6
GPIO output
SARA-R510M8S modules only
GND
TP
0Ω
TP
0Ω
Figure 71: Example of schematic diagram to integrate a SARA-R5 series module using all available interfaces