Ublox SARA-R5 Series

SARA-R5 series - System integration manual
UBX-19041356 - R04 System description Page 8 of 118
C1-Public
1.2 Architecture
Figure 1, Figure 2 and Figure 3 summarize the internal architecture of the SARA-R500S modules,
SARA-R510S modules, and SARA-R510M8S modules, respectively.
V_INT (I/O)
VCC (supply)
ANT_DET
ANT
Flash memory
SIM
I2S
GPIOs
Reset
Power-on
UART
USB
DDC (I2C)
PA
UBX-R5
Cellular chipset
Base Band
processor
Power
Management
Unit
RF transceiver
Filter
Filter
Switch
SPI
SDIO
Secure element
(eSIM)
32 kHz
26 MHz
TCXO
Figure 1: SARA-R500S block diagram
V_INT (I/O)
VCC (supply)
ANT_DET
ANT
Flash memory
SIM
I2S
GPIOs
Reset
Power-on
UART
USB
DDC (I2C)
PA
UBX-R5
Cellular chipset
Base Band
processor
Power
Management
Unit
RF transceiver
Filter
Filter
Switch
SPI
SDIO
Secure element
(eSIM)
RTC
32 kHz
26 MHz
TCXO
Figure 2: SARA-R510S block diagram