AM 320-01-808
16
2. MST8 (Master)
The heart of this board is the CPU 68809. Its address
connections are buffered by IC 18 and IC 19 (HCT541) and
are increased to a CMOS level. IC 10 (HC245) serves the
same function for the data bus. However, this driver is
active only if the memory is addressed externally
(EXTERN). It remains inactive if RAM, ROM or timers
are addressed. IC 15 (SYSROM) contains the System
Program, while the Basic Instruments and Presets are
stored in IC 20 (IROM). RAM IC 14 (6264) is the CPU's
working storage. IC 16 and IC 21(62256) provide 64 k
freely programmable instrument and preset storage. The
three RAMs are battery-buffered to prevent loss of the
memory contents when switching off the power supply.
When the supply voltage is stopped, Q1 and Q2 prevent
undefined voltage levels from reaching the CS input; this
would cause the complete loss of the memory contents. As
displayed in the Memory Map, IC 2 (PAL 16L8) IC 9
(HC138) and IC 3 (HC139) are responsible for the dis-
tribution of the memory areas into RAM, ROM, I/O, etc.
The banking in the lower 16 k of the CPU address region is
controlled by the bank latch IC 6 (HC273) the higher
outputs of which (BS4-B56) are decoded by IC 1
.
To integrate parts of the SYSROM (IC 15) into this address
region, the higher addresses of the SYSROM SA14-SA17
are produced by IC 5 (HC137). Depending on the
PROGRAM signal either the addresses MA 14 and MA 15
are switched through or the bank addresses
BAD14-BAD1 7.
IC 4 (HC137) produces the slave CS signals. The slave
number is written into the latch of the HC137 via MD2-
MD4 with BNKSLV; if addressed, the number appears
decoded in the slave RAM region ($6000. .$67ff) at the
outputs SCSO. .$CS7.
The gates IC 7 (HC32), IC 11 (HCOO), IC 8 and IC 12
(ACOO) produce all control signals required by the system.
The clock for the timers on the slaves (C8M) is produced
on the MST8 as well.
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