WM8804 Production Data
w
PD Rev 4.1 September 2007
10
CONTROL INTERFACE – 2-WIRE MODE
SDIN
SCLK
t
STHO
t
SCY
t
DSU
t
STSU
t
STHO
t
STOP
t
DH
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL MIN TYP MAX UNIT
Program Register Input Information
SCLK cycle time
t
SCY
2500 ns
SCLK duty cycle
40/60 60/40 %
SCLK frequency
400 kHz
Hold Time (Start Condition)
t
STHO
600 ns
Setup Time (Start Condition)
t
STSU
600 ns
Data Setup Time
t
DSU
100 ns
SDIN, SCLK Rise Time
300 ns
SDIN, SCLK Fall Time
300 ns
Setup Time (Stop Condition)
t
STOP
600 ns
Data Hold Time
t
DH
900 ns
SCLK glitch suppression
t
ps
2 8 ns
Table 5 Control Interface Timing – 2-Wire Serial Control Mode