Wolfson WM8804 - Master Clock Timing; Digital Audio Interface - Master Mode

Production Data WM8804
w
PD Rev 4.1 September 2007
7
MASTER CLOCK TIMING
MCLK
t
MCLKL
t
MCLKH
t
MCLKY
Figure 1 Slave Mode MCLK Timing Requirements
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
System Clock Timing Information – Slave Mode
MCLK System clock cycle time
t
MCLKY
27 ns
MCLK System clock pulse width high
t
MCLKH
11 ns
MCLK System clock pulse width low
t
MLCKL
11 ns
MCLK Duty cycle
40:60 60:40 %
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DOUT
LRCLK
t
DL
DIN
t
DDA
t
DHT
t
DST
Figure 2 Digital Audio Data Timing – Master Mode
Test Conditions
PVDD = 3.3V, DVDD = 3.3V, PGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless stated.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Audio Data Input Timing Information
LRCLK propagation delay from
BCLK falling edge
t
DL
0 10 ns
DOUT propagation delay from
BCLK falling edge
t
DDA
0 10 ns
DIN setup time to BCLK rising
edge
t
DST
10 ns
DIN hold time from BCLK rising
edge
t
DHT
10 ns
Table 2 Digital Audio Data Timing – Master Mode