Production Data WM8804
w
PD Rev 4.1 September 2007
25
OSC
CLK
(MHz)
PRE-
SCALE
F
1
(MHz)
F
2
(MHz)
R PLL_N
(Hex)
PLL_K
(Hex)
FREQ
MODE
[1:0]
MCLK
DIV
MCLK
(MHz)
CLKOUT
DIV
[1:0]
CLK
OUT
(MHz)
12 0 12 98.304 8.192 8 C49BA 00 1 24.576 01 49.152
12 0 12 98.304 8.192 8 C49BA 10 0 12.288 00 24.576
12 0 12 98.304 8.192 8 C49BA 10 1 6.144 01 12.288
12 0 12 98.304 8.192 8 C49BA 10 0 12.288 10 6.144
12 0 12 98.304 8.192 8 C49BA 10 1 6.144 11 3.072
24 1 12 90.3168 7.5264 7 21B089 01 0 22.5792 00 45.1584
24 1 12 90.3168 7.5264 7 21B089 10 0 11.2896 00 22.5792
24 1 12 90.3168 7.5264 7 21B089 10 1 5.6448 01 11.2896
24 1 12 90.3168 7.5264 7 21B089 10 0 11.2896 10 5.6448
24 1 12 90.3168 7.5264 7 21B089 10 1 5.6448 11 2.8224
27 1 13.5 98.304 7.2818 7 1208A5 10 0 12.288 01 12.288
27 1 13.5 98.304 7.2818 7 1208A5 10 1 6.144 10 6.144
27 1 13.5 90.3168 6.6901 6 2C2B24 10 0 11.2896 01 11.2896
27 1 13.5 90.3168 6.6901 6 2C2B24 10 1 5.6448 10 5.6448
Table 23 User Mode PLL Configuration Examples
When considering settings not shown in this table, the key configuration parameters which must be
selected for optimum operation are:
• 90MHz ≤ f
2
≤ 100MHz
• 5 ≤ PLL_N ≤ 13
• OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz
PLL INTEGER AND FRACTIONAL CONTROL MODES
The PLL can be operated in either fractional or integer control modes. In PLL User Mode, it is
recommended that the PLL should be operated in fractional control mode at all times. When
the S/PDIF receiver is enabled, the PLL must be operated in fractional control mode.
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
R7
PLL5
07h
2 FRACEN 1 Integer/Fractional PLL Mode
Select
0 = Integer PLL (PLL_N value used,
PLL_K value ignored)
1 = Fractional PLL (both PLL_N and
PLL_K values used)
Note: FRACEN must be set to
enable the fractional PLL when
using S/PDIF Receive Mode.
Table 24 PLL Fractional/Integer Mode Select
MASTER CLOCK (MCLK)
The master clock (MCLK) signal is used to supply reference clock signals to the following circuit
blocks:
• The Digital Audio Interface
• The S/PDIF Transmitter
The master clock (MCLK) pin can be configured as either a clock input or output depending on the
digital audio interface mode as shown in Table 25.
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