Wolfson WM8804 - Page 28

WM8804 Production Data
w
PD Rev 4.1 September 2007
28
The specified f
2
frequencies that must be configured using the PLL_N and PLL_K register values for
reception of specific S/PDIF sample rates are as follows:
• Mode 1 (176.4/192kHz sample rate): f
2
= 98.304MHz
• Modes 2/3/4 (32/44.1/48/88.2/96kHz sample rates): f
2
= 94.3104MHz
The FREQMODE[1:0] bits are automatically controlled by the S/PDIF receiver when the receiver is
enabled and do not need to be configured in any particular initial state by the user before the S/PDIF
receiver is enabled.
Refer to Table 27 and Table 28 for details of MCLKDIV and CLKOUTDIV configuration when the
S/PDIF receiver is enabled.
The PLL register settings are configured by default to allow 32/44.1/48/88.2/96kHz (modes 2/3/4)
sample rate S/PDIF receiver operation using a 12MHz crystal clock. The PLL register settings must
be updated if:
• Any crystal clock frequency other than 12MHz is used.
OR
• A S/PDIF stream with 192kHz sample rate (mode 1) is detected.
In either case, reprogramming of the PLL_N and PLL_K values (and the PRESCALE value,
depending on the crystal frequency) is necessary.
Refer to Table 31 for details of a number of recommended PLL configurations. Many other
configurations are possible; please refer to PLL Configuration section for details regarding how to
calculate alternative settings.
OSC
CLK
(MHz)
PRE-
SCALE
S/PDIF RECEIVER
SAMPLE RATE(S)
(kHz)
F1
(MHz)
F2
(MHz)
R PLL_N
(Hex)
PLL_K
(Hex)
COMMENT
11.2896 0 32 / 44.1 / 48 / 88.2 / 96 11.2896 94.3104 8.3537 8 16A3B3 Set N, K
11.2896 0 192 11.2896 98.304 8.7075 8 2D4766 Set N, K
12 0 32 / 44.1 / 48 / 88.2 / 96 12 94.3104 7.8592 7 36FD21 Default Setting
12 0 192 12 98.304 8.192 8 C49BA Set N, K
12.288 0 32 / 44.1 / 48 / 88.2 / 96 12.288 94.3104 7.675 7 2B3333 Set K
12.288 0 192 12.288 98.304 8 8 0 Set N, K
19.2 1 32 / 44.1 / 48 / 88.2 / 96 9.6 94.3104 9.824 9 346C6A Set Prescale, N, K
19.2 1 192 9.6 98.304 10.24 A F5C28 Set Prescale, N, K
24 1 32 / 44.1 / 48 / 88.2 / 96 12 94.3104 7.8592 7 36FD21 Set Prescale
24 1 192 12 98.304 8.192 8 C49BA Set Prescale, N, K
27 1 32 / 44.1 / 48 / 88.2 / 96 13.5 94.3104 6.986 6 3F19E5 Set Prescale, N, K
27 1 192 13.5 98.304 7.2818 7 1208A5 Set Prescale, K
Table 31 S/PDIF Receive Mode PLL Initial Configuration Examples
The recommended configuration sequences are as follows:
TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:
1. Write appropriate calculated values (relative to oscillator frequency) to PRESCALE,
PLL_N and PLL_K registers for 32/44.1/48/88.2/96kHz (modes 2/3/4) S/PDIF
receiver sample rate operation.
2. Enable PLL by clearing PLLPD bit.
3. Enable S/PDIF receiver by clearing SPDIFRXPD bit.
4. Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF
sample frequency and clocking mode.