Alto Hardware Manual
Section 7: Ethernet
53
ECNTR:
The
number
of
words remammg in the buffer.
EPNTR:
Points at the word prior to that next to
be
processed.
The
task and R registers are shared by
input
and output
so
that
at
any time they are (1) unused, (2)
transmitting a packet,
or
(3) receiving a packet. When
an
Ethernet
SIO
is issued while the Ethernet
microcode
is
reset, the code . dispatches
on
whether
it
is
an
input, output,
or
reset command.
Each Ethernet
SIO
has a result which
is
posted when the
command.
completes.
The
state
of
the
microcode and hardware
at
the time
of
the post is deposited in
EPLOC,
the contents
of
ECNTR
is
deposited in
EELOC,
and the contents
of
EBLOC
is
ORed
into
NWW.
Note
that
resetting the interface with
EBLOC
non-zero will result in an interrupt.
An
input
command
(SIO
with
AcO[14:1S]
= 2) causes the microcode to start
the
input hardware searching
for the start
of
a packet
and
then block. When a packet begins to arrive, the hardware wakes
up
the
microcode which compares the packet's address against the filtering instructions left
in
EHLOC
by the
emulator program. The packet will
be
accepted
if
any
of
three conditions is true: (1)
If
EHLOC
is
zero,
the receiver
is
said to be
promiscuous
- all packets are accepted; (2)
if
the destination address (left byte
of
the first word)
of
the packet is zero, the packet
is
a
broadcast
packet - all receivers accept broadcast
packets; or
(3)
if
the destination byte matches the right byte
of
EHLOC
-
the
packet was sent to
that
specific host.
If
none
of
these conditions is met, the packet
is
rejected
by
restarting
the
receiver, which
causes
it
to ignore the current packet
and
to hunt for the beginning
of
the
next
packet.
If
the packet is
accepted, the microcode enters the
input
main loop.
The
input
main loop first loads
ECl\'TR
and
EPl\'TR
from
EICLOC
and
EIPLOC.
Note
that
EICLOC
and
EIPLOC
are not read until the receiver is committed to transferring data
to
memory, which may
be
long
after the receiver was started; therefore, these locations should
not
be disturbed while the receiver is on.
The main loop repeatedly counts down the buffer size in
ECNTR
and
advances the buffer pointer
in
EPNTR
depositing packet words until either the hardware says that the packet has
ended
or
the buffer
overflows; in either case, the input operation terminates and. posts.
An output command
(SIO
with
AcO[14-1S]
= 1) causes the microcode to compute a random
retransmission interval, wait that long,
and
then start transmitting the
packet
described by
EOCLOC
and
EOPLOC.
The retransmission interval
is
computed by
ANDing
the contents
of
ELLOC
with the contents
of
R37,
the low part
of
the real time clock
(ELLOC
is
not modified).
Then
a one
bit
is left shifted into
ELLOC
and
the high order
bit
of
the result is tested.
If
the high order
bit
is on, the transmission attempt
is
aborted with a 'load overflow' microcode status.
The
above process is repeated each time the
transmitter detects a collision while transmitting the packet.
If
ELLOC
started
out
zero, each collision will
double the value
of
ELLOC,
thus doubling the mean
of
the random
number
generated by
ANDing
ELLOC
with the real time clock.
If
16 consecutive collisions occur without successfully transmitting the packet,
the attempt
is
aborted.
The
retransmission interval is decremented every
38.08
microseconds
(the
memory refresh task wakeup
signal is used for this) until it reaches zero,
at
which time
ECNTR
and
EPNTR
are loaded from
EOCLOC
and
EOPLOC
and
the transmitter
part
of
the interface is started. This
may
occur long after the emulator
program issued the output command, so
EOCLOC
and
EOPLOC
should
not
be
changed while the
transmitter
is
on. Note that
the
mean
of
the first retransmission interval will
be
zero, so the first
transmission attempt will begin immediately. Actual transmission
of
the
packet
does
not
begin until the
BFO
has been filled by the
output
main loop (or
if
the packet is smaller
than
the·
FIFO,
until all
of
the
packet is in the
FIFO)
and there is silence
on
the Ether. IfEICLOC is
non
zero while the transmitter is
counting down a retransmission interval, the receiver is turned
on
and
if
a packet arrives with
an
acceptable address, the transmission attempt is forgotten
and
the microcode enters the
input
main loop as
if
an
input
command
had
been
issued.
The
output
main loop repeatedly counts down the packet length in
ECNTR
and
advances the address in
EPNTR
taking words from the output buffer and putting them
in
the
FIFO.
until
either
the
main memory
buffer is emptied or a hardware condition aborts the operation.
The
output
main
loop
is
awakened for a
To Next Page
Loading...
Need help?
General
