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Hardware Manual Section
7:
Ethernet
52
7.2
Ethernet
Hardware
The Ethernet hardware consists
of
a FIFO buffer, an output shift register· and phase encoder, a clock
recovery circuit, an input shift register, a
eRe
register, and one microcode task. The hardware
is
shown
in
block diagram form in Figure
8.
Packets on the Ether are phase encoded and transmitter
synchronous: it
is
the responsibility
of
the receiver
to
decide where a packet begins (and thus establish
the
phase
of
the data clock), separate the clock
from
the data, and deserialize the incoming bit stream.
The purpose
of
the write register
is
to
synchronize data transfers between the input shift register whose
clock
is
derived from the incoming data, and the FIFO
which
is
synchronous to the processor system
.
clock.
The large FIFO
is
necessary because the Ethernet
task
has
relatively
low
priority, and the worst
case
latency
from
request to task wakeup
is
on the order
of
20
microseconds. The phase encoder uses
the
system
clock
(one Ethernet bit time
is
two
clock periods).
Included in the
clock
recovery section
is
a one-shot which
is
retriggered by each level transition
of
a
passing packet. This detects the envelope
of
a packet and
is
called its 'carrier'. Ethernet phase encoders
mark the beginning
of
a packet
by
prefixing a single 1 bit, called the sync bit, to the front
of
all
transmissions. The leading edge
of
the
sync
bit
of
a packet
will
trigger the carrier one-shot
of
a listening
receiver and establish the receiver clock phase. The sync bit
is
clocked into the input shift register and
recirculated
every
16
bit times thereafter
to
mark the presence
of
a complete word in the register.
If
carrier drops without the sync bit at the end
of
the register, the transmission
was
incomplete, and
is
flagged
in the hardware status bits. When the shift register
is
full,
the word
is
transferred to the write
register
where
it
sits
until the FIFO control
has
synchronized
its
presence and there is room
to
accept it.
If
the shift register
fills
up again before the word
has
been transferred from the write register to the FIFO,
data has been lost and the
.!nput
gata late
flip
flop
is
set.
Ethernet transmitters accumulate a
16
bit
grc1ic
redundancy
.£hecksum
on the data as
it
is
serialized, and
append it
to
an outgoing packet after the last data
word.
As
a receiver deserializes an incoming packet it
recomputes the checksum over the data plus the appended
eRe
word.
If
the resulting receiver checksum
is
non-zero, the received packet
is
assumed
to
be in error, and the condition
is
flagged in the hardware
status byte.
Since
the
eRe
is
of
no
interest
to
the emulator program, a wakeup request to empty data
from
the FIFO
is
only
made when it contains
two
or more
words.
This reduces the effective
size
of
the
FIFO by one
word,
but insures that the
eRe
will
be left behind at the end
of
a packet.
The phase encoder
is
started when the microcode has decremented the countdown to zero, there
is
no
carrier present, and either the
FIFO
is
full,
or
if
the
message
is
less
than
16
words long, all
of
it has been
transferred
to
the
FIFO. The phase encoder
will
not
start up
while
there
is
carrier present. This means
that collisions can only happen because
of
delay
in sensing carrier between widely spaced transmitters.
Collisions
are
detected at the transceiver
by
comparing the data the interface
is
supplying to the
data
being received off the Ether.
If
the
two
are not identical, a
signal
is
returned
to
the interface which sets
the
collision
flip
flop
causing a wakeup request
to
the microcode which resets the interface. Countdowns
are accomplished
by
setting a
flip
flop
from the microcode
which
will
cause a wakeup request on the
next occurrence
of
SWAKMRT.
This makes the grain
size
of
countdowns about
38
microseconds.
The interface and the transceiver are connected together
by
three twisted pairs for signals plus two
supply
voltages
and ground supplied
from
the interface. The signals are
(1)
transmitted data to the
transceiver,
(2)
received data from the transceiver, and
(3)
the collision signal from the transceiver
indicating interference.
7.3
Ethernet Microcode
The Ethernet microcode uses a single task and 2 registers in
R:
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