Alto Hardware Manual
Section
8:
Control
RAM,
ROM,
and s Registers
60
8.6 Interpretation
of
Emulator
Traps
All
unused opcodes except
77400B-77777B
(which is used by Swat, the Alto debugger)
and
61xxxB, where
xxx
is between 0 and
377B,
transfer to microlocation
RAMTRAP
with the instruction
in
L,
the instruction
cycled by 8 bits in the R-register
XREG,
and the emulator's R-register
PC
counted
one
beyond the
trapping instruction:
RAMTRAP:
SWMODE,
:TRAP;
...
TRAP:
:TRAPl;
The result
of
this
is
that
if
your machine has a control
RAM,
these instructions will cause control to enter
it at a location which
is
equal to
TRAPl
in the
ROM
microcode.
If
no
RAM
is present,
the
unimplemented
opcode
will
be handled as described in Section 3.3.
8.7 M and S Registers
The control
RAM
card also includes an M register and
31
S registers.
If
the
3K
RAM
option is installed,
there are 8 banks
of
31
S registers (see below). The M register
is
the analog
of
the basic Alto's L register.
It provides data for the S registers, which are analogous to the basic Alto's R registers. These additional
registers are provided to ease the tight constraint on R register availability which might limit the utility
of
the control
RAM.
The similarities between the M and L registers and between the R and S registers are striking. Both M
and L are loaded from the output
of
the
ALU,
and only
when
_the
Load
L
bit
of
the microinstruction is
active. R registers are loaded from
L,
and S registers are loaded from
M.
Both
Rand
S registers
output
data onto the processor bus. Both R and S registers are addressed
by
the
RSELECT
field
of
the
microinstruction. (Thus the same caveats which apply to the use
of
R37
apply to
S37
(see section
2.3
f).)
Loading and reading
of
both
Rand
S registers are controlled by the
BS
field
of
the microinstruction.
Nevertheless there are considerable differences. To begin with, the M
and
S registers are active only
when a RAM-related task is executing. This means, for example, that in the highest-priority
RAI\1-related
task
it
is
not necessary to save the value
of
M across a
TASK,
since no higher-priority task can change the
value
of
M.
(It is perilous to take advantage
of
this "feature", however, since several non-standard Alto
peripherals make use
of
RAM-related tasks.)
Unlike the data
path
from the L register
to
the R registers, the data
path
from the M register to the S
registers contains no shifter. When an S register is being loaded from
M,
the processor bus receives
an
undefined value rather than being set to zero. The emulator-specific functions
ACSOURCE
and
ACDEST
have no effect
on
S register addressing. And finally, when reading data from the s registers onto the
processor bus, the
RSELECT
value 0 causes the current value
of
the M register
to
appear
on
the bus.
(This explains why there are only
31
useful S registers.)
For
the purposes
of
writing microcode, the S registers are assigned numbers
40B
through
77B,
and appear
to
the microassembler
as
if
they simply extended the R register address space. Hence, for example, the M
register
is
defined as
R40.
In the
3K
RAM
configuration, there are 8 banks
of
31
S registers rather
than
only a single one. Each
RAM-related task has associated with it a 3-bit
register bank number
that
determines which bank is
referenced when a microinstriction specifies that an S register be read
or
loaded. There is
an
emulator
Fl
called
ESRB<-
and a RAM-related
Fl
called
SRB<-
that sets the register
bank
number
for the currently-
executing task from Bus[12-14].
It
is illegal to execute
ESRB<-
or
SRB<-
in
the last cycle before a task
switch; i.e., in the microinstruction after a
TASK
is
executed.
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