Alto Hardware Manual Section
8:
Control
RAM,
ROM,
and s Registers
56
8.0
CONTROL RAM, ROM,
AND
S REGISTERS
In addition to the lK microinstruction
ROM
containing the standard emulator and
I/O
microcode, an Alto
may contain additional microinstruction memory in the form
of
either
ROM
or
RAM;
these are
accompanied by additional registers, called
S registers, whose purpose
and
operation are similar to the
standard R registers.
Several different configurations exist, depending on
the
Alto vintage:
lKRAM
2KROM
3K
RAM
All Altos have
at
least
lK
of
read/write microinstruction memory and one bank
of
31 S
registers. (At one time these were optional_on Alto
!,
but
they are
now
considered standard.)
Certain Alto IIs have
2K
of
read-only microinstruction memory rather than lK. The first
lK
contain the standard emulator and
I/O
microcode, and the second
lK
may
be
programmed
with additional microcode. This configuration includes the
lK
RAM
and
31
S registers
described previously.
Certain other Alto IIs have
3K
of
read/write microinstruction memory
and
8 banks
of
31
S
registers.
8.1
RAM-Related Tasks
The control
RAM
and S registers perform data manipulation
(as
distinct from microcode fetching)
functions in response to certain values
of
the FI and
BS
fields
of
the microinstruction.
Not
all tasks are
likely to· be interested in these functions. Moreover, not· all tasks will have the appropriate values
of
the
F1
and
BS
fields uncommitted. A RAM-related task
is
defined as one during whose execution the control
RA.M:
card will respond
to
FI
and
BS
fields
of
microinstructions. The standard Alto is wired so that the
emulator task
is
the only RAM-related task. At most two other tasks can
be
made RAM-related by a
simple backpanel wiring change.
8.2
Processor Bus and
ALU
Interface
The Alto's
ALU
output and processor bus are each
16
bits wide and its microinstruction bus
is
32
bits
wide, so loading the control
RAM
from the
ALU
output
and
reading the control
RAM
(or
ROM)
onto the
processor bus
is
slightly clumsy.
It
is
done by using the RAM-related
Fl'S
WRTRAM
and
RDRAM (see
Appendix
A).
For
both reading and writing, the control
RAM
address is specified by the control RAM address register
(see Figure
2),
which
is
loaded from the
ALU
output whenever T
is
loaded from its source. This load
may take place
as
late
as
the microinstruction
in
which WRTRAM or RDRAM
is
asserted. The bits
of
the
ALU
output have the following significance
as
a control
RAM
address:
BIT
USE
0-1
Ignored (should
be
zero).
2-
3
BANKSEL
- Selects
RAM
bank in
3K
RAM
configuration; ignored
when
operating
on
ROM.
o
RAMO
1
RAMI
·2
RAM2
3 Undefined
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