Xilinx MicroBlaze User Manual

MicroBlaze Microcontroller Ref Des User Guide www.xilinx.com 11
UG133 January 7, 2005
Additional MicroBlaze and EDK Information
R
Loading the “Calculator_App” Software Application with XMD_STUB
To download and execute the Calculator_App demonstration program, repeat the
procedure in section ‘Loading the “TestApp” Software Application with XMD_STUB’ Start
with step 1 and choose Calculator_App in step 5 instead of Te st App . See Running the
Calculator_App program
Additional MicroBlaze and EDK Information
Congratulations, you have successfully integrated a MicroBlaze Microcontroller into an
FPGA and executed software code.
For additional information on MicroBlaze and the EDK tools, go to
http://support.xilinx.com.

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module