Xilinx MicroBlaze User Manual

MicroBlaze Microcontroller Ref Des User Guide www.xilinx.com 1
UG133 January 7, 2005
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About This Guide
Introduction
This user guide contains information on how to integrate the stand-alone, prebuilt,
MicroBlaze Microcontroller reference design into an FPGA. Although this design is
targeted initially for the Xilinx Spartan-3 Starter Kit Board, the design may be modified
readily for any Xilinx or third party platform.
This guide is an aid in getting started and learning how to use the Xilinx Embedded
Development Kit (EDK) tools. It does this through examples, which show how multiple
software images can be run on a defined soft Microcontroller hardware configuration. This
guide show how an FPGA with a soft processor can be used the same way an engineer
would select an off the shelf microcontroller. This guide will provide examples of a
number of different microcontroller configurations from which an engineer can choose.
The soft microcontroller features and peripherals in the FPGA may be used without
modification, or may be modified and customized using the Xilinx EDK Platform Studio
tools. This guide will cover the flow where multiple software images are load on an
unmodified hardware configuration.
The MicroBaze Microcontroller is an integrated solution intended for implementation of
an embedded controller in FPGA by a user without extensive knowledge of the Xilinx
Embedded Development Kit (EDK) and the Xilinx Platform Studio (XPS). The solution
offered in this document is a minimal implementation that can be expanded easily to
include other peripherals and application software for different usage.
All the necessary documentation, references, HDL code, sample codes, software drivers
and application software are included in the tools or provided with this design.
Guide Contents
This manual contains the following sections:
“Microcontroller Reference Design Overview”
“MicroBlaze Microcontroller Reference Design Number 1”

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module