Xilinx MicroBlaze User Manual

MicroBlaze Microcontroller Ref Des User Guide www.xilinx.com 5
UG133 January 7, 2005
Downloading the Design and Launching XPS
R
Updating and Generation Hardware Files
At this point XPS is open with the selected hardware application. No modifications are
needed to run this design. All the hardware features and peripherals have been pre-loaded
and pre-set. The Hardware Application can run any number of Software Applications.
When the Base System Wizard is used to create a Hardware System, it also will create a
simple Software Application to test the selected Hardware features and peripherals
To be sure that all the Hardware files have been created, in XPS, please select
“Tools>Update Bitstream”. This will run any of the programs needed to generate the
Hardware Application for this reference design.
The message panel should read:
...
Memory Initialization completed successfully.
Done.
Figure Top x-ref 2-2
Figure 2-2: Xilinx Platform Studio (XPS)

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module