Xilinx ML605 User Manual

ML605 Hardware User Guide www.xilinx.com 87
UG534 (v1.2.1) January 21, 2010
NET "FPGA_M0" LOC = "U8"; ## 3 on S2 DIP switch (active-High)
NET "FPGA_M1" LOC = "W8"; ## 4 on S2 DIP switch (active-High)
NET "FPGA_M2" LOC = "V8"; ## 4 on S2 DIP switch (active-High)
NET "FPGA_PROG_B" LOC = "L8"; ## 1 on SW4 pushbutton (active-Low)
NET "FPGA_TCK" LOC = "AE8"; ## 80 on U19
NET "FPGA_TDI" LOC = "AD8"; ## 82 on U19
NET "FPGA_TMS" LOC = "AF8"; ## 85 on U19
NET "FPGA_VBATT" LOC = "N8"; ## 1 on B1 (battery + terminal)
##
NET "GPIO_DIP_SW1" LOC = "D22"; ## 1 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW2" LOC = "C22"; ## 2 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW3" LOC = "L21"; ## 3 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW4" LOC = "L20"; ## 4 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW5" LOC = "C18"; ## 5 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW6" LOC = "B18"; ## 6 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW7" LOC = "K22"; ## 7 on SW1 DIP switch (active-High)
NET "GPIO_DIP_SW8" LOC = "K21"; ## 8 on SW1 DIP switch (active-High)
##
NET "GPIO_LED_0" LOC = "AC22"; ## 2 on LED DS12, 1 on J62
NET "GPIO_LED_1" LOC = "AC24"; ## 2 on LED DS11, 2 on J62
NET "GPIO_LED_2" LOC = "AE22"; ## 2 on LED DS9, 3 on J62
NET "GPIO_LED_3" LOC = "AE23"; ## 2 on LED DS10, 4 on J62
NET "GPIO_LED_4" LOC = "AB23"; ## 2 on LED DS15, 5 on J62
NET "GPIO_LED_5" LOC = "AG23"; ## 2 on LED DS14, 6 on J62
NET "GPIO_LED_6" LOC = "AE24"; ## 2 on LED DS22, 7 on J62
NET "GPIO_LED_7" LOC = "AD24"; ## 2 on LED DS21, 8 on J62
##
NET "GPIO_LED_C" LOC = "AP24"; ## 2 on LED DS16
NET "GPIO_LED_E" LOC = "AE21"; ## 2 on LED DS19
NET "GPIO_LED_N" LOC = "AH27"; ## 2 on LED DS20
NET "GPIO_LED_S" LOC = "AH28"; ## 2 on LED DS18
NET "GPIO_LED_W" LOC = "AD21"; ## 2 on LED DS17
##
NET "GPIO_SW_C" LOC = "G26"; ## 2 on SW9 pushbutton (active-High)
NET "GPIO_SW_E" LOC = "G17"; ## 2 on SW7 pushbutton (active-High)
NET "GPIO_SW_N" LOC = "A19"; ## 2 on SW5 pushbutton (active-High)
NET "GPIO_SW_S" LOC = "A18"; ## 2 on SW6 pushbutton (active-High)
NET "GPIO_SW_W" LOC = "H17"; ## 2 on SW8 pushbutton (active-High)
##
NET "IIC_SCL_DVI" LOC = "AN10"; ## 2 on Q5, 15 on U38
NET "IIC_SCL_MAIN_LS" LOC = "AK9"; ## 2 on Q19
NET "IIC_SCL_SFP" LOC = "AA34"; ## 2 on Q23
NET "IIC_SDA_DVI" LOC = "AP10"; ## 2 on Q6, 14 on U38
NET "IIC_SDA_MAIN_LS" LOC = "AE9"; ## 2 on Q20
NET "IIC_SDA_SFP" LOC = "AA33"; ## 2 on Q21
##
NET "LCD_DB4_LS" LOC = "AD14"; ## 4 on J41
NET "LCD_DB5_LS" LOC = "AK11"; ## 3 on J41
NET "LCD_DB6_LS" LOC = "AJ11"; ## 2 on J41
NET "LCD_DB7_LS" LOC = "AE12"; ## 1 on J41
NET "LCD_E_LS" LOC = "AK12"; ## 9 on J41
NET "LCD_RS_LS" LOC = "T28"; ## 11 on J41
NET "LCD_RW_LS" LOC = "AC14"; ## 10 on J41
##
NET "P30_CS_SEL" LOC = "AJ12"; ## 2 on S2 DIP switch (active-High),1 on U10
##
NET "PCIE_100M_MGT0_N" LOC = "P5"; ## 15 on U14
NET "PCIE_100M_MGT0_P" LOC = "P6"; ## 16 on U14
NET "PCIE_250M_MGT1_N" LOC = "V5"; ## 18 on U9
NET "PCIE_250M_MGT1_P" LOC = "V6"; ## 17 on U9
NET "PCIE_PERST_B_LS" LOC = "AE13"; ## 4 on U32
NET "PCIE_RX0_N" LOC = "J4"; ## B15 on P1
NET "PCIE_RX0_P" LOC = "J3"; ## B14 on P1
NET "PCIE_RX1_N" LOC = "K6"; ## B20 on P1
NET "PCIE_RX1_P" LOC = "K5"; ## B19 on P1

Xilinx ML605 Specifications

General

Brand	Xilinx
Model	ML605
Category	Motherboard
Language	English