Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT - Creating the GTX IBERT Core

VC7203 IBERT Getting Started Guide www.xilinx.com 25
UG847 (v4.0) November 6, 2013
Creating the GTX IBERT Core
Creating the GTX IBERT Core
Vivado Design Suite version 2013.3 is required to rebuild the designs shown here.
This section provides a procedure to create a single Quad GTX IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 113 and 12.5 Gb/s line rate, but
cores for any of the GTX Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to Vivado Design Suite User Guide:
Programming and Debugging (UG908).
1. Start the Vivado Design Suite.
92 Generic 310.000 105 Generic 375.000 118 Generic 440.000
93 Generic 315.000 106 Generic 380.000 119 Generic 445.000
94 Generic 320.000 107 Generic 385.000 120 Generic 450.000
95 Generic 325.000 108 Generic 390.000 121 Generic 455.000
96 Generic 330.000 109 Generic 395.000 122 Generic 460.000
97 Generic 335.000 110 Generic 400.000 123 Generic 465.000
98 Generic 340.000 111 Generic 405.000 124 Generic 470.000
99 Generic 345.000 112 Generic 410.000 125 Generic 475.000
100 Generic 350.000 113 Generic 415.000 126 Generic 480.000
101 Generic 355.000 114 Generic 420.000 127 Generic 485.000
102 Generic 360.000 115 Generic 425.000
Table 1-2: Si570 and Si5368 Frequency Table (Cont’d)
Address Protocol
Frequency
(MHz)
Address Protocol
Frequency
(MHz)
Address Protocol
Frequency
(MHz)
Send Feedback