Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT - Overview

VC7203 IBERT Getting Started Guide www.xilinx.com 5
UG847 (v4.0) November 6, 2013
Overview
Chapter 1
VC7203 IBERT Getting Started Guide
Overview
This document provides a procedure for setting up the VC7203 Virtex®-7 FPGA GTX
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs that are required to run the
IBERT demonstration are stored in a Secure Digital (SD) memory card that is provided
with the VC7203 board. The demonstration shows the capabilities of the Virtex-7
XC7VX485T FPGA GTX transceiver.
The VC7203 board is described in detail in VC7203 Virtex-7 FPGA GTX Transceiver
Characterization Board User Guide (UG957).
The IBERT demonstrations operate one GTX Quad at a time. The procedure consists of:
1. Setting Up the VC7203 Board, page 6
2. Extracting the Project Files, page 7
3. Connecting the GTX Transceivers and Reference Clocks, page 8
4. Configuring the FPGA, page 13
5. Launching the Vivado Design Suite Software, page 14
6. Starting the SuperClock-2 Module, page 16
7. Viewing GTX Transceiver Operation, page 23
8. Closing the IBERT Demonstration, page 23
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