EasyManua.ls Logo

Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT - Viewing GTX Transceiver Operation; Closing the IBERT Demonstration

Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT
44 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
VC7203 IBERT Getting Started Guide www.xilinx.com 23
UG847 (v4.0) November 6, 2013
Running the GTX IBERT Demonstration
Viewing GTX Transceiver Operation
After completing step 6 in Starting the SuperClock-2 Module, the IBERT demonstration is
configured and running. The status and test settings are displayed on the Links tab in the
Links window shown in Figure 1-19.
Note the line rate, TX differential output swing, and error count:
The line rate for all four GTX transceivers is 12.5 Gb/s (see Status in Figure 1-19).
The GTX transmitter differential output swing is preset to 850 mV.
Verify that there are no bit errors.
Additional information on the Vivado Design Suite software and IBERT core can be found
in Vivado Design Suite User Guide: Programming and Debugging (UG908) and LogiCORE IP
Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for Vivado
Design Suite (PG132).
Closing the IBERT Demonstration
To stop the IBERT demonstration:
1. Close the Vivado Design Suite application by selecting File > Exit.
2. Place the main power switch SW1 in the off position.
X-Ref Target - Figure 1-19
Figure 1-19: Serial I/O Analyzer Links
8*BFBB
Send Feedback

Related product manuals