Need help?Do you have a question about the Xilinx Spartan 6 FPGA and is the answer not in the manual?
General| Brand | Xilinx |
|---|---|
| Model | Spartan 6 FPGA |
| Category | Microcontrollers |
| Language | English |
Overview of power management in Spartan-6 FPGAs, focusing on suspend mode.
Compares Spartan-6 suspend mode features to the Extended Spartan-3A family.
Describes the feature allowing wake-up signals from multiple pins.
Explains the SUSPEND_SYNC primitive for synchronizing suspend actions with the design.
Lists the significant features and benefits of the suspend mode.
Outlines the steps required to utilize the suspend feature.
Details the process and block diagram for entering suspend mode.
Describes the four possible ways to exit suspend mode in a powered system.
Explains how the PROGRAM_B pin overrides suspend mode for configuration restart.
Details how to enable the suspend feature and configure glitch filtering.
Explains how to enable and configure multi-pin wake-up.
Describes how to set I/O pin behavior during suspend mode using the SUSPEND attribute.
Explains the SUSPEND attribute for defining pin behavior during suspend.
Provides an example of using the SUSPEND attribute in a UCF file.
Explains how design state is maintained during suspend mode.
Details requirements for preserving application data when entering suspend mode.
Covers programmable timing for waking up from suspend mode.
Discusses selectable clock sources for wake-up timing.
Explains how I/O pins return to normal behavior after suspend.
Describes when the write-protect lock is released from clocked primitives.
Lists configuration pins that remain unaffected during suspend.
Details permitted JTAG operations while the FPGA is in suspend mode.
Describes the functionality and characteristics of the SUSPEND pin.
Explains the programmable glitch filter for the SUSPEND pin.
Describes the SUSPEND_SYNC primitive for suspend request interfacing.
Details the AWAKE pin's role in indicating suspend mode status.
Explains how to control wake-up from an external system.
Discusses synchronizing wake-up across multiple FPGAs or with the system.
Covers limitations related to CRC checking when suspend mode is active.
Specifies voltage requirements for VCCINT, VCCAUX, and VCCO during suspend.
Introduces the multiple voltage supply inputs for Spartan-6 FPGAs.
Describes the internal core supply voltage for logic functions.
Details the auxiliary supply voltage for clock management and I/O resources.
Supply for output buffers in I/O bank 0.
Supply for output buffers in I/O bank 1.
Supply for output buffers in I/O bank 2, connects to configuration source.
Supply for output buffers in I/O bank 3.
Supply for output buffers in I/O bank 4.
Supply for output buffers in I/O bank 5.
Optional input voltage reference supply for HSTL/SSTL standards.
Power supply for transceiver mixed-signal circuitry.
Power supply for transceiver PLL.
Power supply for transceiver TX and RX circuitry.
Power supply for transceiver resistor calibration circuit.
Decryptor key memory backup supply.
Decryptor key EFUSE power supply for programming.
How to set the CONFIG VCCAUX attribute for voltage configuration.
Details the voltage variations and specifications for VCCAUX.
Powers the I/O resources and has separate rails for each bank of I/O.
Discusses importance of PCB design and signal integrity for FPGA systems.
Explains ground or power bounce due to simultaneous output switching.
Importance of PDS design and capacitor usage for FPGA systems.
Introduces lower-power Spartan-6 LX devices and their benefits.
Guides on designing with lower-power Spartan-6 LX devices.
Details specific differences and specifications for lower-power Spartan-6 LX devices.
Overview of FPGA power-up, power-down, and hibernate capabilities.
Explains the built-in power-on reset (POR) circuit and its function.
Discusses the sequence of powering up and down the FPGA supply rails.
Specifies requirements for power supply ramp rates during power-on.
Describes the hot-swap compliance of Spartan-6 FPGAs and I/O features.
Explains how configuration data is retained and effects of brown-out conditions.
Details power-up and power-down procedures for GTP transceivers.
Introduces hibernate mode for maximum power savings.
Steps to put the FPGA into a quiescent state before power removal.
Describes the process of entering the hibernate state for maximum power savings.
Explains how to safely turn off the VCCO supply when entering Hibernate.
Details the steps required to exit the hibernate state and restart operation.
Discusses considerations for various pins and power rails during power transitions.
Introduces Xilinx's power estimation solutions and tools.
Discusses factors for choosing voltage regulators based on FPGA power requirements.
Provides techniques to reduce overall power consumption in FPGA designs.
Explains how to optimize clock routing for reduced power consumption.
Describes automatic power optimization features in the ISE Design Suite.
To Next Page
