Xilinx Spartan 6 FPGA User Manual

24 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
FPGA Voltage Requirements During Suspend Mode
During suspend mode, the V
CCINT
and V
CCAUX
rails must remain powered at the data
sheet levels for Recommended Operating Conditions. However, the V
CCO
supply to each
of the I/O banks can be (potentially) turned off to conserve additional power, depending
on system requirements. Optionally, V
CCO
can be reduced during suspend mode, but this
also affects the voltage levels for any output pin with a SUSPEND attribute set to
DRIVE_LAST_VALUE.
The FPGA's power-on reset (POR) circuit continues to monitor the V
CCINT
and V
CCAUX
supplies. Although V
CCO2
is an input to the POR circuit at initial power-on, the POR circuit
does not monitor the V
CCO
supplies after configuration. By default, if the V
CCINT
or
V
CCAUX
supply dips below the minimum specified data sheet voltage limit, then the FPGA
restarts configuration.
Memory Controller Block
Recommendations and methods for using the memory controller block interface with the
Spartan-6 FPGA suspend mode are found in UG388
, Spartan-6 FPGA Memory Controller
Block User Guide.

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English