Xilinx Spartan 6 FPGA

12 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Exiting Suspend Mode
There are four possible ways to exit suspend mode in a powered system:
• Drive the SUSPEND input Low, exiting suspend mode.
• If multi-pin wake-up mode is enabled, drive the SUSPEND input Low and then assert
any one of the user enabled SCP pins.
• Pulse the PROGRAM_B input Low to reset the FPGA and cause the FPGA to
reprogram.
• Power cycle the FPGA, causing the FPGA to reprogram.
The block diagram in Figure 1-3 shows how to exit suspend mode using the SUSPEND
pin.
When SUSPEND transitions Low, the FPGA automatically re-enables all inputs and
interconnects after a delay of t
SUSPEND_ENABLE
. If using multi-pin wake-up mode,
SUSPEND must first transition Low, then when any of the user enabled SCP pins for
multi-pin wake up mode transition High, the FPGA re-enables all inputs and interconnects
after a delay of t
SUSPEND_ENABLE
.
When enabled in the FPGA bitstream, all flip-flops are optionally globally set or reset
according to the FPGA design description. By default, the flip-flops are not globally set or
reset, which preserves the state of the FPGA application from the beginning of suspend
mode.
The remaining wake-up process depends on two user-programmable timers which define
when FPGA outputs are re-enabled and when the write-protect lock is released from all
writable clocked primitives. These timers begin after the AWAKE pin is High. The
wake-up timing clock source is also programmable.