Xilinx Spartan 6 FPGA User Manual

8 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Suspend Features
The significant features and benefits of the suspend mode:
• Quickly and easily puts the FPGA into a static condition, eliminating most active
current.
• Reduces quiescent current by 40% or more.
• Retains FPGA configuration data and the state of the FPGA application during
suspend mode.
• Fast, programmable FPGA wake-up time from suspend mode.
• Individual control on each user-I/O pin to define pin behavior while in suspend
mode.
• Activated externally by the system using a single dedicated control pin (SUSPEND).
• Indicates the present suspend mode status using the AWAKE pin.
• Awakens an FPGA in suspend mode using any of eight SUSPEND control pins (SCP).
• SUSPEND_SYNC primitive to acknowledge a ready state prior to entering suspend
mode.
Design Steps
To use the suspend feature:
• Enable the Suspend Feature and Glitch Filtering, page 14
• Define the Multi-Pin Wake-Up Feature and Pins, page 15
• Define the I/O Behavior During Suspend Mode, page 15
• Implement steps to maintain application data during suspend mode
(SUSPEND_SYNC) (see Design Requirements to Maintain Application Data, page 17)
• Define the Suspend Mode Wake-Up Timing Controls, page 17
• Define the AWAKE Pin Behavior when Suspend Feature is Enabled, page 21
Entering Suspend Mode
Figure 1-1 is a block diagram of the FPGA entering suspend mode. Figure 1-2, page 10
shows example waveforms.

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English