Xilinx Spartan 6 FPGA User Manual

28 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 2: Voltage Supplies
V
REF
Each I/O bank also has a separate, optional input voltage reference supply, called V
REF
. If
the I/O bank includes an I/O standard that requires a voltage reference such as HSTL or
SSTL, then all V
REF
pins within the I/O bank must be connected to the same voltage. The
V
REF
pins are available as I/O pins if no standards within a bank require them.
Xilinx recommends always separating V
REF
from V
TT
as the V
TT
supply can be very noisy.
A stable V
REF
using a small LDO is the desirable implementation. A voltage divider
implementation is also possible. Knowledge of the PCB environment, such as frequency of
coupled noise, is required to correctly calculate the resistance and capacitance values of the
divider circuit. As a result, an isolated reference supply is usually a more robust and
simpler approach. Refer to UG381
, Spartan-6 FPGA SelectIO Resources User Guide for more
details on V
REF
.
Board Design and Signal Integrity
Building a working system today requires knowledge of the many options available. The
advantages of feature size reduction and reduced power consumption have reduced core
voltages down to the 1.0V range. This change in voltage and signal frequency content
requires the use of advanced design practices to manage electrical effects. The documents
and links on the Xilinx Signal Integrity website provides everything needed to achieve
reliable PCB designs the first time:
http://www.xilinx.com/products/technology/signal-integrity/index.htm
Simultaneously Switching Outputs
Ground or power bounce occurs when a large number of outputs simultaneously switch in
the same direction. Each FPGA family provides guidelines for the recommended
maximum allowable number of simultaneously switching outputs (SSOs). For more
information on SSO, see the Simultaneously Switching Outputs section of UG381
,
Spartan-6 FPGA SelectIO Resources User Guide and DS162
, Spartan-6 FPGA Data Sheet: DC
and Switching Characteristics.
Power Distribution System Design and Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important for all FPGA designs,
especially for high-performance applications greater than 100 MHz. Proper design results
in better overall performance, lower clock jitter, and a generally more robust system.
Before designing the printed circuit board (PCB) for the FPGA design, review UG393
,
Spartan-6 FPGA PCB Design Guide.

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English