Xilinx Spartan 6 FPGA User Manual

Spartan-6 FPGA Power Management www.xilinx.com 15
UG394 (v1.1) September 4, 2012
Enable the Suspend Feature and Glitch Filtering
Define the Multi-Pin Wake-Up Feature and Pins
The multi-pin wake-up feature is not required to use the suspend mode feature. If
multi-pin wake-up is not enabled, suspend mode is enabled and disabled using just the
SUSPEND pin. Multi-pin wake-up is enabled using a BitGen option.
bitgen -g multipin_wakeup:Yes
If multi-pin wake-up is enabled, select which pins are monitored for a rising edge to bring
the FPGA out of suspend mode. Eight SCP pins are used for the multi-pin wake-up
feature. Select from one to eight of these pins to monitor. The SCP pins are dual-purpose
user I/O pins and can be used as general-purpose I/O independent of the suspend
options. Any pins that are not used can be masked out as inputs to the multi-pin wake-up.
The option accepts two hex values for the mask. A value of FF enables all SCP pins, 0F
enables SCP<3..0>.
bitgen -g wakeup_mask:FF
Define the I/O Behavior During Suspend Mode
Use a SUSPEND attribute to define the behavior of each I/O and output pin during
suspend mode.
Single-Ended I/O Standards
Each output, open-drain output, or bidirectional I/O pin in the FPGA application that uses
a single-ended I/O standard can be individually programmed for one of the suspend
mode behaviors shown in Table 1-2. The default behavior is for a high impedance pin
during suspend mode although other options are available.
Differential I/O Standards
The output drivers for the LVDS, RSDS, mini-LVDS, PPDS, and TMDS differential I/O
standards are high impedance, using any of the 3STATE attributes described in Table 1-2.
The DRIVE_LAST_VALUE attribute is not supported for differential output drivers.
Treat the pseudo-differential I/O standards, such as BLVDS, DIFF_HSTL, and DIFF_SSTL,
as two single-ended I/O pins. All the attributes apply as for Single-Ended I/O Standards
Table 1-2: Output Behavior Options during Suspend Mode
SUSPEND Attribute Function
DRIVE_LAST_VALUE
The output continues to drive the level that was last stored in the output latch, according
to the chosen standard. Requires V
CCO
to remain at the recommended operating conditions
for the bank.
3STATE
(default)
The output is in the high-impedance state with no active internal pull-up or pull-down
resistor. Results in the lowest possible I/O current draw.
3STATE_PULLUP
The output is in the high-impedance state with an internal pull-up resistor to the associated
V
CCO
supply. Requires V
CCO
to remain at the recommended operating conditions for the
bank.
3STATE_PULLDOWN The output is in the high-impedance state with an internal pull-down resistor to GND.
3STATE_KEEPER
The output is high impedance. The internal bus keeper circuit is active. Requires V
CCO
to
remain at the recommended operating conditions for the bank.

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English