Xilinx Spartan 6 FPGA User Manual

16 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
although for any differential standard the settings must be set appropriately for both pins
of the complementary pair.
When in the high-impedance state, the differential driver pair does not conduct current to
the power or ground rails, or between adjacent pins.
SUSPEND Attribute
The SUSPEND attribute allows each pin to have an individually defined behavior during
suspend mode. The available options are listed in Table 1-2.
UCF Example
This UCF constraint example defines the suspend mode behavior for a specific pin. The
SUSPEND attribute can be included on the same UCF line as other constraints for a pin.
Net "<net_name>" SUSPEND = "io_type" ;
UCF entries for a single-ended pin and a differential pair are shown in the following
example:
NET "TX<0>" IOSTANDARD = LVCMOS_33 | SUSPEND = "DRIVE_LAST_VALUE" ;
NET "TX_P<0>" IOSTANDARD = LVDS_33 | SUSPEND = "3STATE_PULLUP" ;
NET "TX_N<0>" IOSTANDARD = LVDS_33 | SUSPEND = "3STATE_PULLDOWN" ;
Design Maintained during Suspend Mode
After entering suspend mode, all writable clocked primitives are write-protected after a
delay of t
SUSPEND_GWE
. The state of all clocked memory primitives is maintained during
suspend mode.
• Logic block flip-flops
• I/O block latches and flip-flops
• Logic block distributed RAM (LUT RAM)
• Logic block shift registers (SRL)
• Block RAM and registers
When exiting suspend mode, all writable clocked primitives are re-enabled, controlled by
the sw_gwe_cycle setting.
An additional bitstream option, en_sw_gsr, controls whether all clocked primitives are
globally set or reset when the FPGA awakens from suspend mode. By default,
en_sw_gsr:No signifies that clocked primitives are not set or reset when the FPGA
awakens and all states are preserved.

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English