Xilinx Spartan 6 FPGA User Manual

Spartan-6 FPGA Power Management www.xilinx.com 7
UG394 (v1.1) September 4, 2012
Chapter 1
Power Management With Suspend Mode
Introduction
Some applications require the lowest possible system cost or highest performance, and
other applications require the lowest possible standby power. Spartan®-6 FPGAs offer
low-power options to balance these cost and performance trade-offs.
The Spartan-6 family offers the suspend mode, an advanced static power-management
feature, which reduces FPGA power consumption while retaining the FPGA's
configuration data and maintaining the design. The device can quickly enter and exit
suspend mode as required in an application.
Differences from Extended Spartan-3A Family
The suspend mode in Spartan-6 FPGAs is a superset of the suspend feature in the
Extended Spartan-3A FPGAs. Two new enhancements include multi-pin wake-up and
suspend synchronization.
Multi-Pin Wake-up
The multi-pin wake-up feature allows the FPGA to monitor for a wake-up signal on up to
eight pins. In the Extended Spartan-3A family, monitoring was limited to the SUSPEND
pin itself. Multi-pin wake-up also allows a number of independent sources to trigger the
FPGA to return to the normal application.
Suspend Synchronization
The Spartan-6 FPGA primitive, SUSPEND_SYNC, enables the synchronization of the
suspend action with the application design. In the Extended Spartan-3A family, the
suspend mode activation begins immediately upon asserting the SUSPEND pin. The
Spartan-6 FPGA SUSPEND_SYNC primitive allows the application design to
acknowledge a suspend request, thereby allowing the application to finish necessary
functions prior to entering the suspend mode.

Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English