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Xilinx SP605 User Manual

Xilinx SP605
70 pages
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SP605 Hardware
User Guide
UG526 (v1.9) February 14, 2019

Table of Contents

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Xilinx SP605 Specifications

General IconGeneral
BrandXilinx
ModelSP605
CategoryMotherboard
LanguageEnglish

Summary

Revision History

Preface: About This Guide

Guide Contents

Lists chapters and appendices in the manual.

Additional Documentation

Lists related documents for download.

Chapter 1: SP605 Evaluation Board

Overview

Introduces the SP605 board and its purpose.

Additional Information

Lists resources available for the SP605 board.

Features

Lists the key hardware features of the SP605 board.

Block Diagram

Provides a high-level block diagram of the SP605.

Related Xilinx Documents

Lists resources for additional Xilinx documentation.

Electrostatic Discharge Caution

Provides essential ESD prevention procedures.

Detailed Description

Spartan-6 XC6SLX45T-3FGG484 FPGA

Describes the main FPGA chip on the SP605 board.

I/O Voltage Rails

Explains the voltage rails for the FPGA I/O banks.

128 MB DDR3 Component Memory

Details the DDR3 memory module on the board.

SPI x4 Flash

Explains the SPI flash memory for configuration.

Linear BPI Flash

Describes the Linear BPI flash memory.

System ACE CF and CompactFlash Connector

Covers the System ACE CF controller and CF card slot.

USB JTAG

Details the USB-to-JTAG interface for configuration.

Clock Generation

Explains the clock sources available on the board.

Multi-Gigabit Transceivers (GTP MGTs)

Describes the MGTs for high-speed serial communication.

PCI Express Endpoint Connectivity

Details the PCIe interface on the board.

SFP Module Connector

Describes the SFP connector for network modules.

10/100/1000 Tri-Speed Ethernet PHY

Explains the Ethernet PHY.

USB-to-UART Bridge

Covers the USB-to-UART serial interface.

DVI CODEC

Describes the DVI video output connector.

IIC Bus

Explains the IIC communication interfaces.

Status LEDs

Details the general status LEDs on the board.

Ethernet PHY Status LEDs

Describes specific LEDs for Ethernet status.

FPGA INIT and DONE LEDs

Explains LEDs related to FPGA configuration status.

User I/O

Introduces general-purpose user I/O capabilities.

Switches

Covers the various switches on the board.

VITA 57.1 FMC LPC Connector

Describes the FMC connector.

Power Management

Covers board power supply details.

Configuration Options

Lists the methods for configuring the FPGA.

Appendix A: Default Jumper and Switch Settings

Table A-33: Default Switch Settings

Lists default settings for DIP switches.

Table A-34: Default Jumper Settings

Lists default settings for jumpers.

Appendix B: VITA 57.1 FMC LPC Connector Pinout

Appendix C: Xilinx Design Constraints

Overview

Introduces XDC file templates for the SP605.

Appendix D: Regulatory and Compliance Information

CE Directives

Lists relevant EU directives.

CE Standards

Lists relevant CE standards.

Electromagnetic Compatibility

Details EMC requirements and classification.

Safety

Lists safety standards.

Appendix E: References

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