Xilinx SP605 - USB-to-UART Bridge

36 www.xilinx.com SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
Chapter 1: SP605 Evaluation Board
12. USB-to-UART Bridge
The SP605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U4) which
allows connection to a host computer with a USB cable. The USB cable is supplied in this
evaluation kit (Type A end to host computer, Type Mini-B end to SP605 connector J23).
Table 1-16 details the SP605 J23 pinout.
Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS
UART Lite). The FPGA supports the USB-to-UART bridge using four signal pins: Transmit
(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).
Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the
CP2103GM USB-to-UART bridge to appear as a COM port to host computer
communications application software (for example, HyperTerm or TeraTerm). The VCP
device driver must be installed on the host PC prior to establishing communications with
the SP605. Refer to the evaluation kit Getting Started Guide for driver installation
instructions.
Refer to the Silicon Labs
website for technical information on the CP2103GM and the VCP
drivers.
In addition, see some of the Xilinx UART IP specifications at:
•
XPS UART Lite (DS571) [Ref 13]
•
XPS 16550 UART (DS577) [Ref 14]
Table 1-16: USB Type B Pin Assignments and Signal Definitions
USB Connector
Pin
Signal Name Description
1 VBUS +5V from host system (not used)
2 USB_DATA_N Bidirectional differential serial data (N-side)
3 USB_DATA_P Bidirectional differential serial data (P-side)
4 GROUND Signal ground
Table 1-17: USB-to-UART Connections
U1 FPGA Pin
UART Function
in FPGA
Schematic Net
Name
U30 CP2103GM
Pin
UART Function
in CP2103GM
F18 RTS, output USB_1_CTS 22 CTS, input
F19 CTS, input USB_1_RTS 23 RTS, output
B21 TX, data out USB_1_RX 24 RXD, data in
H17 RX, data in USB_1_TX 25 TXD, data out
Notes:
1. The schematic net names correspond with the CP2103GM pin names and functions, and the UART IP
in the FPGA must be connected accordingly.