Name: Xilinx Spartan 6 FPGA
Brand: Xilinx
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Spartan-6 FPGA Power Management www.xilinx.com 13

UG394 (v1.1) September 4, 2012

Exiting Suspend Mode

X-Ref Target - Figure 1-3

Figure 1-3: Exiting Suspend Mode

SUSPEND

Attribute

SUSPEND

Attribute

Wake-Up

Timing Clock

Source

Glitch Filter

Suspend Enable

SRL

LUT RAM

Flip-Flops

Latches

Block RAM

Writable Clocked Primitives

FPGA Application Logic

FPGA

Inputs

FPGA

Outputs

Re-enable

FPGA Inputs

Set/Reset

Flip-Flops

SUSPEND

AWAKE

Enable

Unlock Clocked

Primitives

Activate Outputs

sw_clk

en_sw_gsr

ENABLE_SUSPEND

sw_gts_cycle

sw_gwe_cycle

Filter Select

1 1,024

1,024

UG394_c1_03_020310

drive_awake

multipin_wakeup

edge detector

wakeup_mask<0>

edge detector

wakeup_mask<1>

edge detector

wakeup_mask<7>

SCP0

SCP1

SCP7

Multi-Pin Wake-up

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Xilinx Spartan 6 FPGA Specifications

General

Brand	Xilinx
Model	Spartan 6 FPGA
Category	Microcontrollers
Language	English

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Xilinx Spartan 6 FPGA Specifications

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