Yamaha RX-A710 - Page 73

Pin
No.
Port Name Function Name
Related Power Supply
Detail of FunctionON OFF
I/O Logic I/O Logic
42
IIO1_0/TXD8/N_SS2/
N_RTS2/N_CTS2/V/
TA1IN/P7_3
DK1_N_IPDET I L act O Low Dock iPod detect
43
CLK2/V/TA1OUT/
P7_2
SR_PON O H act O Low SIRIUS power supply control
44
MSCL/IEIN/ISRXD2/
OUTC2_2/IIO1_7/
STXD2/SCL2/RXD2/
TA0IN/TB5IN/P7_1
SR_MISO I Data O Low SIRIUS reception data
45
TA0OUT/TXD2/
SDA2/SRXD2/
IIO1_6/OUTC2_0/
ISTXD2/IEOUT/
MSDA/P7_0
SR_MOSI O Data O Low SIRIUS transmission data
46
TXD1/SDA1/SRXD1/
P6_7
232C_DBG_MOSI O Data O Low RS-232C transmission data / Debug / E8a
47 P14_7 DSP_PON O H act O Low DSP power supply
48
RXD1/SCL1/STXD1/
P6_6
232C_DBG_MISO I Data O Low RS-232C reception data / Debug / E8a
49 P11_7 DAC_N_CS O L act O Low DAC chip select (SW of V3071, FP DAC is D-FF)
50 CLK1/P6_5 DBG_SCK I Clock O Low E8a
51
N_CTS1/N_RTS1/
N_SS1/OUTC2_1/
ISCLK2/P6_4
DBG_BUSY O O Low E8a
52
TXD0/SDA0/SRXD0/
P6_3
DSP_MOSI O Data O Low DSP/DIR/DAC transmission data
53
TB2IN/RXD0/SCL0/
STXD0/P6_2
DSP_MISO I Data I --- DSP/DIR/DAC reception data
54 TB1IN/CLK0/P6_1 DSP_SCK O Clock O Low DSP/DIR/DAC communication clock
55
TB0IN/N_CTS0/N_
RTS0/N_SS0/P6_0
NCPU_N_INT I H act O Low Network microprocessor interrupt
56 P19_5 --- I --- I --- No used (+3.3DSP is applied, input port setting)
57
D31/OUTC2_7/
P13_7
DSP1_N_RST O L act O Low DSP1 reset
58
D30/OUTC2_1/
ISCLK2/P13_6
EX_SCK O Clock O Low FL/EEPROM/ expansion IO communication clock
59
D29/OUTC2_2/IS-
RXD2/IEIN/P13_5
EEP_MISO I Data O Low EEPROM reception data
60
D28/OUTC2_0/
ISTXD2/IEOUT/
P13_4
EX_MOSI O Data O Low FL/EEPROM/ expansion IO transmission data
61 P19_4 EEP_N_CS O L act O Low EEPROM chip select
62
RDY/CS3/N_CTS7/
N_RTS7/P5_7
FPGA_N_CS B Bus O Low External bus FPGA chip select
63 ALE/CS2/RXD7/P5_6 DFF2_N_CS B Bus O Low External bus DFF2 chip select
64 HOLD/CLK7/P5_5 DBG_EPM I I --- E8a
65
HLD
A/CS1/TXD7/
P5_4
DFF1_N_CS B Bus O Low External bus DFF1 chip select
66
D27/OUTC2_3/
P13_3
--- O Low O Low No used
67 VSS VSS ---
68
D26/OUTC2_6/
P13_2
DSP1_N_SPIRDY I L act O Low DSP1 SPI ready
69 VCC VCC ---
70
D25/OUTC2_5/
P13_1
DSP2_N_CS O L act O Low DSP2 chip select
71
D24/OUTC2_4/
P13_0
DSP1_N_CS O L act O Low DSP1 chip select
72 CLKOUT/BCLK/P5_3 NC(BCLK) B Bus O Low External bus
73 RD/P5_2 MCBUS_N_RD B Bus O Low External bus
74 WR1/BC1/P5_1 NC(BC1) B Bus O Low External bus
75 WR0/WR/P5_0
MCBUS_N_WR B Bus I --- External bus
DBG_N_CE I I --- E8a
76 D23/P12_7 MT_DA O H act O Low Mute Digital Audio
77 D22/P12_6 DIR_N_CS O L act O Low DIR chip select
78 D21/P12_5 DIR_N_RST O L act O Low DIR reset
73
RX-V671/HTR-6064/RX-A710
RX-V671/HTR-6064/
RX-A710
DRAFT