Yamaha RX-A710 - Page 74

Pin
No.
Port Name Function Name
Related Power Supply
Detail of FunctionON OFF
I/O Logic I/O Logic
79 P19_3 DK1_AP I L act I --- iPod accessory power
80 P17_3 DK1_PON O H act O Low Dock power supply
81 P17_2 UAW_PON O H act O Low UAW power supply control
82 P17_1 NCPU_PON O H act O Low NET/USB power supply
83 P17_0 NET_SEL_M O H NET O Low Main USB/NET select
84 P19_2 NET_SEL_Z O H NET O Low Zone USB/NET select
85
CS0/A23/TXD6/
SDA6/SRXD6/P4_7
FLASH_N_CS O L act O Low External bus Flash ROM chip select
86
CS1/A22/RXD6/
SCL6/STXD6/P4_6
A[22] B Bus O Low External bus
87 CS2/A21/CLK6/P4_5 A[21] B Bus O Low External bus
88
CS3/A20/N_CTS6/N_
RTS6/N_SS6/P4_4
A[20] B Bus O Low External bus
89
A19/TXD3/SDA3/
SRXD3/OUTC2_0/
ISTXD2/IEOUT/P4_3
A[19] B Bus O Low External bus
90 P11_6 --- O Low O Low Spare
91
A18/RXD3/SCL3/
STXD3/ISRXD2/IEIN/
P4_2
A[18] B Bus O Low External bus
92 P11_5 --- O Low O Low Spare
93 A17/CLK3/P4_1 A[17] B Bus O Low External bus
94
A16/N_CTS3/N_
RTS3/N_SS3/P4_0
A[16] B Bus O Low External bus
95 P16_7/TXD10 DK_MOSI O Data O Low Dock UART transmission data
96 P16_6/RXD10 DK_MISO I Data I --- Dock UART reception data (3.3V logic input)
97 P16_5/CLK10 R32C_N_INT O L act O Low Interrupt of R32C to Blackfin
98
P16_4/N_CTS10/N_
RTS10
BF_MT I H act O Low Mute signal from Blackfin (NCPU_N_INT distinction use)
99
A15/[A15/D15]/TA4IN/
U/P3_7
A[15] B Bus O Low External bus
100
A14/[A14/D14]/
TA4OUT/U/P3_6
A[1
4] B Bus O Low External bus
101
A13/[A13/D13]/TA2IN/
W/P3_5
A[13] B Bus O Low External bus
102
A12/[A12/D12]/
TA2OUT/W/P3_4
A[12] B Bus O Low External bus
103 P16_3/TXD9 NCPU_PIC_MISO O Data O Low Network microprocessor SPI transmission data
104 P16_2/RXD9 NCPU_PIC_MOSI I Data O Low Network microprocessor SPI reception data
105 P16_1/CLK9 NCPU_PIC_SCK I Clock O Low Network microprocessor SPI communication clock
106
P16_0/N_CTS9/N_
RTS9
NCPU_N_RST O L act O Low Network microprocessor reset
107
A11/[A11/D11]/TA1IN/
V/P3_3
A[11] B Bus O Low External bus
108
A10/[A10/D10]/
TA1OUT/V/P3_2
A[10] B Bus O Low External bus
109
A9/[A9/D9]/TA3OUT/
UD0B/UD1B/P3_1
A[9] B Bus O Low External bus
110 D20/P12_4 --- O Low O Low Spare
111
D19/N_CTS6/N_
RTS6/N_SS6/P12_3
--- O Low O Low Spare
112
D18/RXD6/SCL6/
STXD6/P12_2
--- O Low O Low Spare (After FPGA Config, I2C is possible)
113 D17/CLK6/P12_1 FPGA_SCK O Clock O Low FPGA clock (at Boot)
114
D16/TXD6/SDA6/
SRXD6/P12_0
FPGA_MOSI O Data O Low FPGA transmission data (at Boot)
115 VCC VCC ---
116
A8/[A8/D8]/TA0OUT/
UD0A/UD1A/P3_0
A[8] B Bus O Low External bus
117 VSS VSS ---
118
A7/[A7/D7]/AN2_7/
P2_7/TXD10
A[7] B Bus O Low External bus
119
A6/[A6/D6]/AN2_6/
P2_6/RXD10
A[6] B Bus O Low External bus
120
A5/[A5/D5]/AN2_5/
P2_5/CLK10
A[5] B Bus O Low External bus
74
RX-V671/HTR-6064/RX-A710
RX-V671/HTR-6064/
RX-A710
DRAFT